From 26feb3a83d605a9f2302266d524e6e443d31d197 Mon Sep 17 00:00:00 2001
From: Andrew Cagney <cagney@redhat.com>
Date: Thu, 21 May 1998 09:32:07 +0000
Subject: Fix sign extension on 32 bit add/sub instructions.

---
 sim/mips/ChangeLog |  5 +++++
 sim/mips/mips.igen | 60 ++++++++++++++++++++++++++++++++++++++----------------
 2 files changed, 47 insertions(+), 18 deletions(-)

(limited to 'sim/mips')

diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog
index 2afcd49..ca50e36 100644
--- a/sim/mips/ChangeLog
+++ b/sim/mips/ChangeLog
@@ -1,3 +1,8 @@
+Thu May 21 18:57:19 1998  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* sim-main.h (ALU32_END): Sign extend 32 bit results.
+	* mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
+	
 start-sanitize-r5900
 Thu May 21 17:15:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 
diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen
index a1f254c..df89140 100644
--- a/sim/mips/mips.igen
+++ b/sim/mips/mips.igen
@@ -272,9 +272,13 @@
 *tx19:
 // end-sanitize-tx19
 {
-  ALU32_BEGIN (GPR[RS]);
-  ALU32_ADD (GPR[RT]);
-  ALU32_END (GPR[RD]);
+  TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
+  {
+    ALU32_BEGIN (GPR[RS]);
+    ALU32_ADD (GPR[RT]);
+    ALU32_END (GPR[RD]);
+  }
+  TRACE_ALU_RESULT (GPR[RD]);
 }
 
 
@@ -297,9 +301,13 @@
 *tx19:
 // end-sanitize-tx19
 {
-  ALU32_BEGIN (GPR[RS]);
-  ALU32_ADD (EXTEND16 (IMMEDIATE));
-  ALU32_END (GPR[RT]);
+  TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
+  {
+    ALU32_BEGIN (GPR[RS]);
+    ALU32_ADD (EXTEND16 (IMMEDIATE));
+    ALU32_END (GPR[RT]);
+  }
+  TRACE_ALU_RESULT (GPR[RT]);
 }
 
 
@@ -923,9 +931,13 @@
 // end-sanitize-tx19
 {
   /* this check's for overflow */
-  ALU64_BEGIN (GPR[RS]);
-  ALU64_ADD (GPR[RT]);
-  ALU64_END (GPR[RD]);
+  TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
+  {
+    ALU64_BEGIN (GPR[RS]);
+    ALU64_ADD (GPR[RT]);
+    ALU64_END (GPR[RD]);
+  }
+  TRACE_ALU_RESULT (GPR[RD]);
 }
 
 
@@ -948,9 +960,13 @@
 *tx19:
 // end-sanitize-tx19
 {
-  ALU64_BEGIN (GPR[RS]);
-  ALU64_ADD (EXTEND16 (IMMEDIATE));
-  ALU64_END (GPR[RT]);
+  TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
+  {
+    ALU64_BEGIN (GPR[RS]);
+    ALU64_ADD (EXTEND16 (IMMEDIATE));
+    ALU64_END (GPR[RT]);
+  }
+  TRACE_ALU_RESULT (GPR[RT]);
 }
 
 
@@ -1554,9 +1570,13 @@
 *tx19:
 // end-sanitize-tx19
 {
-  ALU64_BEGIN (GPR[RS]);
-  ALU64_SUB (GPR[RT]);
-  ALU64_END (GPR[RD]);
+  TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
+  {
+    ALU64_BEGIN (GPR[RS]);
+    ALU64_SUB (GPR[RT]);
+    ALU64_END (GPR[RD]);
+  }
+  TRACE_ALU_RESULT (GPR[RD]);
 }
 
 
@@ -3105,9 +3125,13 @@
 *tx19:
 // end-sanitize-tx19
 {
-  ALU32_BEGIN (GPR[RS]);
-  ALU32_SUB (GPR[RT]);
-  ALU32_END (GPR[RD]);
+  TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
+  {
+    ALU32_BEGIN (GPR[RS]);
+    ALU32_SUB (GPR[RT]);
+    ALU32_END (GPR[RD]);
+  }
+  TRACE_ALU_RESULT (GPR[RD]);
 }
 
 
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