From a3027dd7480cbc4d681fa75bcd3ca2cabc6022a4 Mon Sep 17 00:00:00 2001 From: "Frank Ch. Eigler" Date: Thu, 2 Mar 2000 18:14:02 +0000 Subject: * autoconf correction * merge from internal repo -> sourceware 2000-03-02 Frank Ch. Eigler * configure: Regenerated. Tue Feb 8 18:35:01 2000 Donald Lindsay * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf calls, conditional on the simulator being in verbose mode. --- sim/mips/mips.igen | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) (limited to 'sim/mips/mips.igen') diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen index 78998b0..3589b31 100644 --- a/sim/mips/mips.igen +++ b/sim/mips/mips.igen @@ -3031,7 +3031,13 @@ else if ((FS & 0x1) == 0) PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS])); else - PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0); + { + if (STATE_VERBOSE_P(SD)) + sim_io_eprintf (SD, + "Warning: PC 0x%x: semantic_DMxC1_COP1Sa 32-bit use of odd FPR number\n", + CIA); + PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0); + } } } 010001,00,X,01,5.RT,5.FS,00000000000:COP1Sb:64::DMxC1 @@ -3055,7 +3061,12 @@ else if ((FS & 0x1) == 0) GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS]; else - GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0; + { + if (STATE_VERBOSE_P(SD)) + sim_io_eprintf (SD, + "Warning: PC 0x%x: DMxC1 32-bit use of odd FPR number\n", CIA); + GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0; + } } } @@ -3194,7 +3205,12 @@ if (X) { /*MTC1*/ if (SizeFGR() == 64) - PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT]))); + { + if (STATE_VERBOSE_P(SD)) + sim_io_eprintf (SD, + "Warning: PC 0x%x: MTC1 not DMTC1 with 64 bit regs\n", CIA); + PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT]))); + } else PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT])); } -- cgit v1.1