From 06c441cceffb1437a3af51bfad43dce5fd200d9e Mon Sep 17 00:00:00 2001 From: Faraz Shahbazker Date: Wed, 2 Feb 2022 11:17:25 +0100 Subject: sim: mips: Add simulator support for mips32r6/mips64r6 2022-02-01 Ali Lown Andrew Bennett Dragan Mladjenovic Faraz Shahbazker sim/common/ChangeLog: * sim-bits.h (EXTEND9, EXTEND18 ,EXTEND19, EXTEND21, EXTEND26): New macros. sim/mips/ChangeLog: * Makefile.in (IGEN_INCLUDE): Add mips3264r6.igen. * configure: Regenerate. * configure.ac: Support mipsisa32r6 and mipsisa64r6. (sim_engine_run): Pick simulator model from processor specified in e_flags. * cp1.c (value_fpr): Handle fmt_dc32. (fp_unary, fp_binary): Zero initialize locals. (update_fcsr, fp_classify, fp_rint, fp_r6_cmp, inner_fmac, fp_fmac, fp_min, fp_max, fp_mina, fp_maxa, fp_fmadd, fp_fmsub): New functions. (sim_fpu_class_mips_mapping): New. * cp1.h (fcsr_ABS2008_mask, fcsr_ABS2008_shift): New define. * interp.c (MIPSR6_P): New. (load_word): Allow unaligned memory access for MIPSR6. * micromips.igen (sc, scd): Adapt to new do_sc* helper signature. * mips.igen: Add *r6 models. (signal_if_cti, forbiddenslot32): New helpers. (delayslot32): Use signal_if_cti. (do_sc, do_scd); Add store_ll_bit parameter. (sc, scd): Adapt to previous change. (nal, beq, bal): New definitions for *r6. (sll): Split nop and ssnop cases into ... (nop, ssnop): New definitions. (loadstore_ea): Use the 32-bit compatibility adressing. (cache): Split logic into ... (do_cache): New helper. (check_fpu): Select IEEE 754-2008 mode for R6. (not_word_value, unpredictable, check_mt_hilo, check_mf_hilo, check_multi_hilo, check_div_hilo, check_u64, do_dmfc1b, add, li, addu, and, andi, bgez, bgtz, blez, bltz, bne, break, dadd, daddiu, daddu, dror, dror32, drorv, dsll, dsll32, dsllv, dsra, dsra32, dsrav, dsrl, dsrl32, dsub, dsubu, j, jal, jalr, jalr.hb, lb, lbu, ld, lh, lhu, lui, lw, lwu, nor, or, ori, ror, rorv, sb, sd, sh, sll, sllv, slt, slti, sltiu, sltu, sra, srav, srl, srlv, sub, subu, sw, sync, syscall, teq, tge, tgeu, tlt, tltu, tne, xor, xori, check_fmt_p, do_load_double, do_store_double, abs.FMT, add.FMT, ceil.l.FMT, ceil.w.FMT, cfc1, ctc1, cvt.d.FMT, cvt.l.FMT, cvt.w.FMT, div.FMT, dfmc1, dmtc1, floor.l.FMT, floor.w.FMT, ldc1, lwc1, mfc1, mov.FMT, mtc1, mul.FMT, recip.FMT, round.l.FMT, round.w.FMT, rsqrt.FMT, sdc1, sqrt.FMT, sub.FMT, swc1, trunc.l.FMT, trunc.w.FMT, bc0f, bc0fl, bc0t, bc0tl, dmfc0, dmtc0, eret, mfc0, mtc0, cop, tlbp, tlbr, tlbwi, tlbwr): Enable on *r6 models. * mips3264r2.igen (dext, dextm, dextu, di, dins, dinsm, dinsu, dsbh, dshd, ei, ext, mfhc1, mthc1, ins, seb, seh, synci, rdhwr, wsbh): Likewise. * mips3264r6.igen: New file. * sim-main.h (FP_formats): Add fmt_dc32. (FORBIDDEN_SLOT): New macros. (simFORBIDDENSLOT, FP_R6CMP_*, FP_R6CLASS_*): New defines. (fp_r6_cmp, fp_classify, fp_rint, fp_min, fp_max, fp_mina, fp_maxa, fp_fmadd, fp_fmsub): New declarations. (R6Compare, Classify, RoundToIntegralExact, Min, Max, MinA, MaxA, FusedMultiplyAdd, FusedMultiplySub): New macros. Wrapping previous declarations. sim/testsuite/mips/ChangeLog: * basic.exp: Add r6-*.s tests. (run_r6_removed_test): New function. (run_endian_tests): New function. * hilo-hazard-3.s: Skip for mips*r6. * r2-fpu.s: New test. * r6-64.s: New test. * r6-branch.s: New test. * r6-forbidden.s: New test. * r6-fpu.s: New test. * r6-llsc-dp.s: New test. * r6-llsc-wp.s: New test. * r6-removed.csv: New test. * r6-removed.s: New test. * r6.s: New test. * utils-r6.inc: New inc. --- sim/mips/mips.igen | 380 ++++++++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 359 insertions(+), 21 deletions(-) (limited to 'sim/mips/mips.igen') diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen index b0c5e59..dfad422 100644 --- a/sim/mips/mips.igen +++ b/sim/mips/mips.igen @@ -46,8 +46,10 @@ :model:::mipsV:mipsisaV: :model:::mips32:mipsisa32: :model:::mips32r2:mipsisa32r2: +:model:::mips32r6:mipsisa32r6: :model:::mips64:mipsisa64: :model:::mips64r2:mipsisa64r2: +:model:::mips64r6:mipsisa64r6: // Vendor ISAs: // @@ -102,7 +104,28 @@ -// Helper: +// Helpers: +// +// Check if given instruction is CTI, if so signal +// +:function:::void:signal_if_cti:instruction_word instr +{ + uint32_t maj = (instr & 0xfc000000) >> 26; + uint32_t special = instr & 0x3f; + if ((maj & 0x3e) == 0x06 /* Branch/Jump */ + || ((maj & 0x38) == 0 && !((maj & 0x6) == 0)) + || maj == 0x18 + || (maj & 0x37) == 0x32 + || (maj & 0x37) == 0x36 + || ((maj == 0) && (special == 0x9)) + /* DERET/ERET/WAIT */ + || ((maj == 0x10) && (instr & 0x02000000) + && (special == 0x1f || special == 0x18 || special == 0x20))) + { + SignalException (ReservedInstruction, instr); + } +} + // // Simulate a 32 bit delayslot instruction // @@ -115,12 +138,34 @@ CIA = CIA + 4; /* NOTE not mips16 */ STATE |= simDELAYSLOT; delay_insn = IMEM32 (CIA); /* NOTE not mips16 */ + signal_if_cti (SD_, delay_insn); ENGINE_ISSUE_PREFIX_HOOK(); idecode_issue (CPU_, delay_insn, (CIA)); STATE &= ~simDELAYSLOT; return target; } +// +// Simulate a 32 bit forbidden slot instruction +// + +:function:::address_word:forbiddenslot32: +*mips32r6: +*mips64r6: +{ + instruction_word delay_insn; + sim_events_slip (SD, 1); + DSPC = CIA; + CIA = CIA + 4; + STATE |= simFORBIDDENSLOT; + delay_insn = IMEM32 (CIA); + signal_if_cti (SD_, delay_insn); + ENGINE_ISSUE_PREFIX_HOOK (); + idecode_issue (CPU_, delay_insn, (CIA)); + STATE &= ~simFORBIDDENSLOT; + return CIA + 4; +} + :function:::address_word:nullify_next_insn32: { sim_events_slip (SD, 1); @@ -142,6 +187,7 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *vr4100: *vr5000: *r3900: @@ -154,6 +200,7 @@ *mips64: *mips64r2: *micromips64: +*mips64r6: { #if 0 /* XXX FIXME: enable this only after some additional testing. */ /* If in user mode and UX is not set, use 32-bit compatibility effective @@ -184,10 +231,12 @@ *r3900: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: *micromips32: *micromips64: +*mips64r6: { #if WITH_TARGET_WORD_BITSIZE == 64 return value != (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); @@ -219,10 +268,12 @@ :function:::void:unpredictable: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: *micromips32: *micromips64: +*mips64r6: { unpredictable_action (CPU, CIA); } @@ -311,8 +362,10 @@ :function:::int:check_mt_hilo:hilo_history *history *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *r3900: *micromips32: *micromips64: @@ -337,8 +390,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -411,8 +466,10 @@ :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *r3900: *micromips32: *micromips64: @@ -468,10 +525,12 @@ :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: *micromips32: *micromips64: +*mips64r6: { int64_t time = sim_events_time (SD); hi->op.timestamp = time; @@ -507,8 +566,10 @@ *mips64r2: *mips32: *mips32r2: +*mips32r6: *micromips64: *micromips32: +*mips64r6: { #if 0 /* XXX FIXME: enable this only after some additional testing. */ if (UserMode && (SR & (status_UX|status_PX)) == 0) @@ -1081,7 +1142,7 @@ } } -:function:::void:do_sc:int rt, int offsetarg, int basereg, address_word instruction_0 +:function:::void:do_sc:int rt, int offsetarg, int basereg, address_word instruction_0, int store_ll_bit { uint32_t instruction = instruction_0; address_word base = GPR[basereg]; @@ -1111,12 +1172,13 @@ if (LLBIT) StoreMemory (AccessLength_WORD, memval, memval1, paddr, vaddr, isREAL); - GPR[rt] = LLBIT; + if (store_ll_bit) + GPR[rt] = LLBIT; } } } -:function:::void:do_scd:int rt, int roffset, int rbase +:function:::void:do_scd:int rt, int roffset, int rbase, int store_ll_bit { address_word base = GPR[rbase]; address_word offset = EXTEND16 (roffset); @@ -1137,7 +1199,8 @@ if (LLBIT) StoreMemory (AccessLength_DOUBLEWORD, memval, memval1, paddr, vaddr, isREAL); - GPR[rt] = LLBIT; + if (store_ll_bit) + GPR[rt] = LLBIT; } } } @@ -1376,6 +1439,7 @@ *mipsV: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -1633,6 +1697,7 @@ *mipsII: *mips32: *mips32r2: +*mips32r6: *micromips32: { check_fpu (SD_); @@ -1763,8 +1828,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -1812,8 +1879,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -1841,8 +1910,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -1868,8 +1939,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -1888,8 +1961,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -1922,6 +1997,17 @@ } +000100,5.RS,5.RT,16.OFFSET:R6:32::BEQ +"beq r, r, " +*mips32r6: +*mips64r6: +{ + address_word offset = EXTEND16 (OFFSET) << 2; + if (GPR[RS] == GPR[RT]) + DELAY_SLOT (NIA + offset); + else + FORBIDDEN_SLOT (); +} 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL "beql r, r, " @@ -1957,8 +2043,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -1997,7 +2085,15 @@ } } - +000001,00000,10001,16.OFFSET:REGIMM:32::BAL +"bal " +*mips32r6: +*mips64r6: +{ + address_word offset = EXTEND16 (OFFSET) << 2; + RA = (CIA + 8); + DELAY_SLOT (NIA + offset); +} 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL "bgezall r, " @@ -2063,8 +2159,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -2114,8 +2212,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -2165,8 +2265,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -2209,6 +2311,18 @@ +000001,00000,10000,16.OFFSET:REGIMM:32::NAL +"nal " +*mips32r6: +*mips64r6: +{ + address_word offset = EXTEND16 (OFFSET) << 2; + RA = (CIA + 8); + FORBIDDEN_SLOT (); +} + + + 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL "bltzall r, " *mipsII: @@ -2273,8 +2387,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -2322,8 +2438,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -2370,6 +2488,7 @@ *mipsV: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: { @@ -2409,6 +2528,7 @@ *mipsV: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: { @@ -2432,6 +2552,7 @@ *mipsV: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: { @@ -2450,6 +2571,8 @@ if (RT != RD) Unpredictable (); check_u64 (SD_, instruction_0); + if (RT != RD) + Unpredictable (); do_dclo (SD_, RD, RS); } @@ -2464,6 +2587,8 @@ if (RT != RD) Unpredictable (); check_u64 (SD_, instruction_0); + if (RT != RD) + Unpredictable (); do_dclz (SD_, RD, RS); } @@ -2771,6 +2896,7 @@ 000000,00001,5.RT,5.RD,5.SHIFT,111010::64::DROR "dror r, r, " *mips64r2: +*mips64r6: *vr5400: *vr5500: { @@ -2781,6 +2907,7 @@ 000000,00001,5.RT,5.RD,5.SHIFT,111110::64::DROR32 "dror32 r, r, " *mips64r2: +*mips64r6: *vr5400: *vr5500: { @@ -2791,6 +2918,7 @@ 000000,5.RS,5.RT,5.RD,00001,010110::64::DRORV "drorv r, r, r" *mips64r2: +*mips64r6: *vr5400: *vr5500: { @@ -2813,6 +2941,7 @@ *mipsV: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: { @@ -2828,6 +2957,7 @@ *mipsV: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: { @@ -2850,6 +2980,7 @@ *mipsV: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: { @@ -2872,6 +3003,7 @@ *mipsV: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: { @@ -2887,6 +3019,7 @@ *mipsV: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: { @@ -2910,6 +3043,7 @@ *mipsV: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: { @@ -2932,6 +3066,7 @@ *mipsV: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: { @@ -2947,6 +3082,7 @@ *mipsV: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: { @@ -2972,6 +3108,7 @@ *mipsV: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: { @@ -2987,6 +3124,7 @@ *mipsV: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: { @@ -3009,6 +3147,7 @@ *mipsV: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: { @@ -3026,8 +3165,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -3048,8 +3189,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -3071,8 +3214,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -3086,7 +3231,9 @@ "jalr.hb r":RD == 31 "jalr.hb r, r" *mips32r2: +*mips32r6: *mips64r2: +*mips64r6: { address_word temp = GPR[RS]; GPR[RD] = CIA + 8; @@ -3102,8 +3249,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -3114,7 +3263,9 @@ 000000,5.RS,0000000000,10000,001000:SPECIAL:32::JR_HB "jr.hb r" *mips32r2: +*mips32r6: *mips64r2: +*mips64r6: { DELAY_SLOT (GPR[RS]); } @@ -3232,8 +3383,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -3251,8 +3404,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -3268,6 +3423,7 @@ *mipsV: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: { @@ -3335,8 +3491,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -3354,8 +3512,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -3405,8 +3565,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -3424,8 +3586,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -3498,6 +3662,7 @@ *mipsV: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: { @@ -3882,8 +4047,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -3908,8 +4075,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -3935,8 +4104,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -3973,7 +4144,9 @@ 000000,00001,5.RT,5.RD,5.SHIFT,000010::32::ROR "ror r, r, " *mips32r2: +*mips32r6: *mips64r2: +*mips64r6: *smartmips: *vr5400: *vr5500: @@ -3984,7 +4157,9 @@ 000000,5.RS,5.RT,5.RD,00001,000110::32::RORV "rorv r, r, r" *mips32r2: +*mips32r6: *mips64r2: +*mips64r6: *smartmips: *vr5400: *vr5500: @@ -4086,8 +4261,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -4109,7 +4286,7 @@ *vr4100: *vr5000: { - do_sc (SD_, RT, OFFSET, BASE, instruction_0); + do_sc (SD_, RT, OFFSET, BASE, instruction_0, 1); } @@ -4124,7 +4301,7 @@ *vr5000: { check_u64 (SD_, instruction_0); - do_scd (SD_, RT, OFFSET, BASE); + do_scd (SD_, RT, OFFSET, BASE, 1); } @@ -4135,6 +4312,7 @@ *mipsV: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: { @@ -4200,8 +4378,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -4239,16 +4419,16 @@ 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLb "nop":RD == 0 && RT == 0 && SHIFT == 0 "ssnop":RD == 0 && RT == 0 && SHIFT == 1 +"ehb":RD == 0 && RT == 0 && SHIFT == 3 "sll r, r, " *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: { - /* Skip shift for NOP and SSNOP, so that there won't be lots of - extraneous trace output. */ - if (RD != 0 || RT != 0 || (SHIFT != 0 && SHIFT != 1)) - do_sll (SD_, RT, RD, SHIFT); + do_sll (SD_, RT, RD, SHIFT); } @@ -4270,8 +4450,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -4296,8 +4478,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -4322,8 +4506,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -4348,8 +4534,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -4375,8 +4563,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -4404,8 +4594,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -4435,8 +4627,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -4465,8 +4659,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -4495,8 +4691,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -4514,8 +4712,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -4542,8 +4742,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -4561,8 +4763,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *r3900: *vr5000: @@ -4637,8 +4841,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -4656,8 +4862,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -4674,8 +4882,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: { @@ -4708,8 +4918,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: { @@ -4759,8 +4971,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: { @@ -4776,8 +4990,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: { @@ -4827,8 +5043,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: { @@ -4844,8 +5062,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: { @@ -4886,8 +5106,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -4912,8 +5134,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -4996,6 +5220,8 @@ *mipsIII: *mipsIV: *mips32: +*mips32r6: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -5051,10 +5277,27 @@ if (! COP_Usable (1)) SignalExceptionCoProcessorUnusable (1); - FCSR &= ~fcsr_NAN2008_mask; + FCSR &= ~(fcsr_NAN2008_mask | fcsr_ABS2008_mask); sim_fpu_quiet_nan_inverted = true; } +// Helper: +// +// Check that the FPU is currently usable, and signal a CoProcessorUnusable +// exception if not. +// + +:function:::void:check_fpu: +*mips32r6: +*mips64r6: +{ + if (! COP_Usable (1)) + SignalExceptionCoProcessorUnusable (1); + + FCSR |= (fcsr_NAN2008_mask | fcsr_ABS2008_mask); + sim_fpu_quiet_nan_inverted = 0; + sim_fpu_set_mode (sim_fpu_ieee754_2008); +} // Helper: // @@ -5067,6 +5310,7 @@ *mipsII: *mips32: *mips32r2: +*mips32r6: *micromips32: { int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian); @@ -5102,6 +5346,7 @@ *mips32: *mips32r2: *micromips32: + *mips32r6: { int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian); address_word vaddr; @@ -5131,8 +5376,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -5151,8 +5398,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -5263,8 +5512,10 @@ *mipsIV: *mipsV: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -5281,8 +5532,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -5328,8 +5581,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: { do_cfc1 (SD_, RT, FS); } @@ -5365,8 +5620,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: { do_ctc1 (SD_, RT, FS); } @@ -5384,8 +5641,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -5400,8 +5659,10 @@ *mipsIV: *mipsV: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -5433,8 +5694,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -5474,8 +5737,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -5493,8 +5758,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -5526,6 +5793,7 @@ *mipsV: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -5561,6 +5829,7 @@ *mipsV: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -5577,8 +5846,10 @@ *mipsIV: *mipsV: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -5595,8 +5866,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -5610,6 +5883,7 @@ *mipsII: *mips32: *mips32r2: +*mips32r6: { check_fpu (SD_); COP_LD (1, FT, do_load_double (SD_, GPR[BASE], EXTEND16 (OFFSET))); @@ -5623,6 +5897,7 @@ *mipsV: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -5684,8 +5959,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -5740,8 +6017,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -5759,8 +6038,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -5869,8 +6150,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -5888,8 +6171,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -5907,8 +6192,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -6005,8 +6292,10 @@ *mipsIV: *mipsV: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr5000: { do_recip_fmt (SD_, FMT, FD, FS); @@ -6019,8 +6308,10 @@ *mipsIV: *mipsV: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -6037,8 +6328,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -6052,8 +6345,10 @@ *mipsIV: *mipsV: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr5000: { do_rsqrt_fmt (SD_, FMT, FD, FS); @@ -6065,6 +6360,7 @@ *mipsII: *mips32: *mips32r2: +*mips32r6: { do_sdc1 (SD_, FT, OFFSET, BASE); } @@ -6077,6 +6373,7 @@ *mipsV: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -6088,7 +6385,7 @@ 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:32,f::SDXC1 "sdxc1 f, r(r)" -*mips32r2 +*mips32r2: { check_fpu (SD_); do_store_double (SD_, GPR[BASE], GPR[INDEX], COP_SD (1, FS)); @@ -6137,8 +6434,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -6156,8 +6455,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -6176,8 +6477,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -6205,8 +6508,10 @@ *mipsIV: *mipsV: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -6223,8 +6528,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -6249,8 +6556,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: @@ -6272,8 +6581,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: @@ -6287,8 +6598,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: @@ -6301,11 +6614,23 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: +:function:::void:do_cache:int op, int rbase, int roffset, address_word instruction_0 +{ + address_word base = GPR[rbase]; + address_word offset = EXTEND16 (roffset); + { + address_word vaddr = loadstore_ea (SD_, base, offset); + address_word paddr = vaddr; + CacheOp(op, vaddr, paddr, instruction_0); + } +} 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE "cache , (r)" @@ -6320,13 +6645,7 @@ *vr5000: *r3900: { - address_word base = GPR[BASE]; - address_word offset = EXTEND16 (OFFSET); - { - address_word vaddr = loadstore_ea (SD_, base, offset); - address_word paddr = vaddr; - CacheOp(OP, vaddr, paddr, instruction_0); - } + do_cache (SD_, OP, BASE, OFFSET, instruction_0); } @@ -6337,6 +6656,7 @@ *mipsV: *mips64: *mips64r2: +*mips64r6: { check_u64 (SD_, instruction_0); DecodeCoproc (instruction_0, 0, cp0_dmfc0, RT, RD, SEL); @@ -6350,6 +6670,7 @@ *mipsV: *mips64: *mips64r2: +*mips64r6: { check_u64 (SD_, instruction_0); DecodeCoproc (instruction_0, 0, cp0_dmtc0, RT, RD, SEL); @@ -6363,8 +6684,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: { @@ -6392,8 +6715,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -6412,8 +6737,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -6446,8 +6773,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *r3900: { @@ -6465,8 +6794,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: @@ -6480,8 +6811,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: @@ -6495,8 +6828,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: @@ -6510,13 +6845,16 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: :include:::mips3264r2.igen +:include:::mips3264r6.igen :include:::m16.igen :include:::m16e.igen :include:::mdmx.igen -- cgit v1.1