From 8e394ffc7ab691eafcf276d7ae578454a8c5548f Mon Sep 17 00:00:00 2001 From: Andrew Bennett Date: Fri, 25 Sep 2015 15:52:18 +0100 Subject: [PATCH] Add micromips support to the MIPS simulator 2015-09-25 Andrew Bennett Ali Lown sim/common/ * sim-bits.h (EXTEND6): New macro. (EXTEND12): New macro. (EXTEND25): New macro. sim/mips/ * Makefile.in (tmp-micromips): New rule. (tmp-mach-multi): Add support for micromips. * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim that works for both mips64 and micromips64. (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and micromips32. Add build support for micromips. * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc, do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv, do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu, do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv, do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append, do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions. Refactored instruction code to use these functions. * dsp2.igen: Refactored instruction code to use the new functions. * interp.c (decode_coproc): Refactored to work with any instruction encoding. (isa_mode): New variable (RSVD_INSTRUCTION): Changed to 0x00000039. * m16.igen (BREAK16): Refactored instruction to use do_break16. (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models. * micromips.dc: New file. * micromips.igen: New file. * micromips16.dc: New file. * micromipsdsp.igen: New file. * micromipsrun.c: New file. * mips.igen (do_swc1): Changed to work with any instruction encoding. (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc, do_scd do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu, do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt, do_add_fmt do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1, do_cvt_d_fmt do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl, do_cvt_s_pu do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt, do_luxc1_32 do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b, do_mov_fmt, do_movtf do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt, do_mtc1b, do_mul_fmt do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps, do_plu_ps, do_pul_ps do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt, do_prefx, do_sdc1 do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt, do_swc1, do_swxc1 do_trunc_fmt): New functions, refactored from existing instructions. Refactored instruction code to use these functions. (RSVD): Changed to use new reserved instruction. (loadstore_ea, not_word_value, unpredictable, check_mt_hilo, check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32, do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double, do_store_double): Added micromips32 and micromips64 models. Added include for micromips.igen and micromipsdsp.igen Add micromips32 and micromips64 models. (DecodeCoproc): Updated to use new macro definition. * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di, do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu, do_seb, do_seh do_rdhwr, do_wsbh): New functions. Refactored instruction code to use these functions. * sim-main.h (CP0_operation): New enum. (DecodeCoproc): Updated macro. (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE, MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16, MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and ISA_MODE_MICROMIPS): New defines. (sim_state): Add isa_mode field. sim/testsuite/sim/mips/ * basic.exp (run_micromips_test, run_sim_tests): New functions Add support for micromips tests. * hilo-hazard-4.s: New file. * testutils.inc (_dowrite): Changed reserved instruction encoding. (writemsg): Moved the la and li instructions before the data they are assigned to, which prevents a bug where MIPS32 relocations are used instead of micromips relocations when building for micromips. --- sim/mips/micromips.igen | 3091 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 3091 insertions(+) create mode 100644 sim/mips/micromips.igen (limited to 'sim/mips/micromips.igen') diff --git a/sim/mips/micromips.igen b/sim/mips/micromips.igen new file mode 100644 index 0000000..2c62376 --- /dev/null +++ b/sim/mips/micromips.igen @@ -0,0 +1,3091 @@ +// Simulator definition for the micromips ASE. +// Copyright (C) 2005-2015 Free Software Foundation, Inc. +// Contributed by Imagination Technologies, Ltd. +// Written by Andrew Bennett +// +// This file is part of the MIPS sim. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +:compute:::int:TBASE:BASE:((BASE < 2) ? (16 + BASE) \: BASE) +:compute:::int:TRD:RD:((RD < 2) ? (16 + RD) \: RD) +:compute:::int:TRS:RS:((RS < 2) ? (16 + RS) \: RS) +:compute:::int:TRT:RT:((RT < 2) ? (16 + RT) \: RT) +:compute:::int:TRT_S:RT_S:((RT_S == 1 ) ? 17 \: RT_S) +:compute:::int:ERT:RT:(compute_movep_src_reg (SD_, RT)) +:compute:::int:ERS:RS:(compute_movep_src_reg (SD_, RS)) + +:compute:::int:IMM_DEC1:IMMEDIATE:((IMMEDIATE == 7) ? -1 \: ((IMMEDIATE == 0) ? 1 \: IMMEDIATE << 2)) +:compute:::int:IMM_DEC2:IMMEDIATE:((IMMEDIATE < 8) ? IMMEDIATE \: (IMMEDIATE - 16)) +:compute:::int:IMM_DEC3:IMMEDIATE:((IMMEDIATE < 2) ? IMMEDIATE + 256 \: ((IMMEDIATE < 256) ? IMMEDIATE \: ((IMMEDIATE < 510) ? IMMEDIATE - 512 \: IMMEDIATE - 768))) +:compute:::int:IMM_DEC4:IMMEDIATE:(compute_andi16_imm (SD_, IMMEDIATE)) +:compute:::int:IMM_DEC5:IMMEDIATE:((IMMEDIATE < 15) ? IMMEDIATE \: -1) +:compute:::int:IMM_DEC6:IMMEDIATE:((IMMEDIATE < 127) ? IMMEDIATE \: -1) + +:compute:::int:SHIFT_DEC:SHIFT:((SHIFT == 0) ? 8 \: SHIFT) + +:compute:::int:IMM_SHIFT_1BIT:IMMEDIATE:(IMMEDIATE << 1) +:compute:::int:IMM_SHIFT_2BIT:IMMEDIATE:(IMMEDIATE << 2) + +:function:::address_word:delayslot_micromips:address_word target, address_word nia, int delayslot_instruction_size +{ + instruction_word delay_insn; + sim_events_slip (SD, 1); + DSPC = CIA; + CIA = nia; + STATE |= simDELAYSLOT; + ENGINE_ISSUE_PREFIX_HOOK(); + micromips_instruction_decode (SD, CPU, CIA, delayslot_instruction_size); + STATE &= ~simDELAYSLOT; + return target; +} + +:function:::address_word:process_isa_mode:address_word target +{ + SD->isa_mode = target & 0x1; + return (target & (-1 << 1)); +} + +:function:::address_word:do_micromips_jalr:int rt, int rs, address_word nia, int delayslot_instruction_size +{ + GPR[rt] = (nia + delayslot_instruction_size) | ISA_MODE_MICROMIPS; + return (process_isa_mode (SD_, + delayslot_micromips (SD_, GPR[rs], nia, delayslot_instruction_size))); +} + +:function:::address_word:do_micromips_jal:address_word target, address_word nia, int delayslot_instruction_size +{ + RA = (nia + delayslot_instruction_size) | ISA_MODE_MICROMIPS; + return delayslot_micromips (SD_, target, nia, delayslot_instruction_size); +} + + +:function:::unsigned32:compute_movep_src_reg:int reg +{ + switch(reg) + { + case 0: return 0; + case 1: return 17; + case 2: return 2; + case 3: return 3; + case 4: return 16; + case 5: return 18; + case 6: return 19; + case 7: return 20; + default: return 0; + } +} + +:function:::unsigned32:compute_andi16_imm:int encoded_imm +{ + switch (encoded_imm) + { + case 0: return 128; + case 1: return 1; + case 2: return 2; + case 3: return 3; + case 4: return 4; + case 5: return 7; + case 6: return 8; + case 7: return 15; + case 8: return 16; + case 9: return 31; + case 10: return 32; + case 11: return 63; + case 12: return 64; + case 13: return 255; + case 14: return 32768; + case 15: return 65535; + default: return 0; + } +} + +:function:::FP_formats:convert_fmt_micromips:int fmt +{ + switch (fmt) + { + case 0: return fmt_single; + case 1: return fmt_double; + case 2: return fmt_ps; + default: return fmt_unknown; + } +} + +:function:::FP_formats:convert_fmt_micromips_cvt_d:int fmt +{ + switch (fmt) + { + case 0: return fmt_single; + case 1: return fmt_word; + case 2: return fmt_long; + default: return fmt_unknown; + } +} + + +:function:::FP_formats:convert_fmt_micromips_cvt_s:int fmt +{ + switch (fmt) + { + case 0: return fmt_double; + case 1: return fmt_word; + case 2: return fmt_long; + default: return fmt_unknown; + } +} + + +011011,3.RD,6.IMMEDIATE,1:POOL16E:16::ADDIUR1SP +"addiur1sp r, " +*micromips32: +*micromips64: +{ + do_addiu (SD_, SPIDX, TRD, IMMEDIATE << 2); +} + + +011011,3.RD,3.RS,3.IMMEDIATE,0:POOL16E:16::ADDIUR2 +"addiur2 r, r, " +*micromips32: +*micromips64: +{ + do_addiu (SD_, TRS, TRD, IMM_DEC1); +} + + +010011,5.RD,4.IMMEDIATE,0:POOL16D:16::ADDIUS5 +"addius5 r, " +*micromips32: +*micromips64: +{ + do_addiu (SD_, RD, RD, IMM_DEC2); +} + + +010011,9.IMMEDIATE,1:POOL16D:16::ADDIUSP +"addiusp " +*micromips32: +*micromips64: +{ + do_addiu (SD_, SPIDX, SPIDX, IMM_DEC3 << 2); +} + + +000001,3.RD,3.RT,3.RS,0:POOL16A:16::ADDU16 +"addu16 r, r, r" +*micromips32: +*micromips64: +{ + do_addu (SD_, TRS, TRT, TRD); +} + + +001011,3.RD,3.RS,4.IMMEDIATE:MICROMIPS:16::ANDI16 +"andi16 r, r, " +*micromips32: +*micromips64: +{ + do_andi (SD_, TRS, TRD, IMM_DEC4); +} + + +010001,0010,3.RT,3.RS:POOL16C:16::AND16 +"and16 r, r" +*micromips32: +*micromips64: +{ + do_and (SD_, TRS, TRT, TRT); +} + + +110011,10.IMMEDIATE:MICROMIPS:16::B16 +"b16 " +*micromips32: +*micromips64: +{ + NIA = delayslot_micromips (SD_, NIA + (EXTEND11 (IMMEDIATE << 1)), + NIA, MICROMIPS_DELAYSLOT_SIZE_ANY); +} + + +100011,3.RS,7.IMMEDIATE:MICROMIPS:16::BEQZ16 +"beqz16 r, " +*micromips32: +*micromips64: +{ + if (GPR[TRS] == 0) + NIA = delayslot_micromips (SD_, NIA + (EXTEND8 (IMMEDIATE << 1)), + NIA, MICROMIPS_DELAYSLOT_SIZE_ANY); +} + + +101011,3.RS,7.IMMEDIATE:MICROMIPS:16::BNEZ16 +"bnez16 r, " +*micromips32: +*micromips64: +{ + if (GPR[TRS] != 0) + NIA = delayslot_micromips (SD_, NIA + (EXTEND8 (IMMEDIATE << 1)), + NIA, MICROMIPS_DELAYSLOT_SIZE_ANY); +} + + +010001,101000,4.CODE:POOL16C:16::BREAK16 +"break16 %#lx" +*micromips32: +*micromips64: +{ + do_break16 (SD_, instruction_0); +} + + +010001,01110,5.RS:POOL16C:16::JALR16 +"jalr16 r" +*micromips32: +*micromips64: +{ + NIA = do_micromips_jalr (SD_, RAIDX, RS, NIA, MICROMIPS_DELAYSLOT_SIZE_32); +} + + +010001,01111,5.RS:POOL16C:16::JALRS16 +"jalrs16 r" +*micromips32: +*micromips64: +{ + NIA = do_micromips_jalr (SD_, RAIDX, RS, NIA, MICROMIPS_DELAYSLOT_SIZE_16); +} + + +010001,01100,5.RS:POOL16C:16::JR16 +"jr16 r" +*micromips32: +*micromips64: +{ + NIA = process_isa_mode (SD_, + delayslot_micromips (SD_, GPR[RS], NIA, MICROMIPS_DELAYSLOT_SIZE_ANY)); +} + + +010001,11000,5.IMMEDIATE:POOL16C:16::JRADDIUSP +"jraddiusp " +*micromips32: +*micromips64: +{ + address_word temp = RA; + do_addiu (SD_, SPIDX, SPIDX, IMMEDIATE << 2); + NIA = process_isa_mode (SD_, temp); +} + + +010001,01101,5.RS:POOL16C:16::JRC +"jrc r" +*micromips32: +*micromips64: +{ + NIA = process_isa_mode (SD_, GPR[RS]); +} + + +000010,3.RT,3.BASE,4.IMMEDIATE:MICROMIPS:16::LBU16 +"lbu16 r, (r)" +*micromips32: +*micromips64: +{ + /* LBU can have a negative offset. As the offset argument to do_load is + unsigned we need to do the address calcuation before the function call so + that the load address has been correctly calculated */ + + GPR[TRT] = do_load (SD_, AccessLength_BYTE, GPR[TBASE] + IMM_DEC5, 0); +} + + +001010,3.RT,3.BASE,4.IMMEDIATE:MICROMIPS:16::LHU16 +"lhu16 r, (r)" +*micromips32: +*micromips64: +{ + GPR[TRT] = do_load (SD_, AccessLength_HALFWORD, GPR[TBASE], IMM_SHIFT_1BIT); +} + + +111011,3.RD,7.IMMEDIATE:MICROMIPS:16::LI16 +"li16 r, " +*micromips32: +*micromips64: +{ + GPR[TRD] = IMM_DEC6; +} + + +011010,3.RT,3.BASE,4.IMMEDIATE:MICROMIPS:16::LW16 +"lw16 r, (r)" +*micromips32: +*micromips64: +{ + GPR[TRT] = EXTEND32 ( + do_load (SD_, AccessLength_WORD, GPR[TBASE], IMM_SHIFT_2BIT)); +} + +:%s::::LWMREGS:int lwmregs +*micromips32: +*micromips64: +{ + if (lwmregs == 3) + return "s0, s1, s2, s3, ra"; + else if (lwmregs == 2) + return "s0, s1, s2, ra"; + else if (lwmregs == 1) + return "s0, s1, ra"; + else if (lwmregs == 0) + return "s0, ra"; + else + return ""; +} + +010001,0100,2.LWMREGS,4.IMMEDIATE:POOL16C:16::LWM16 +"lwm16 %s, (sp)" +*micromips32: +*micromips64: +{ + int address = GPR[SPIDX] + IMM_SHIFT_2BIT; + int reg_offset; + + for (reg_offset = 0; reg_offset <= LWMREGS; reg_offset++) + GPR[16 + reg_offset] = EXTEND32 ( + do_load (SD_, AccessLength_WORD, address, reg_offset * 4)); + + RA = EXTEND32 (do_load (SD_, AccessLength_WORD, address, reg_offset * 4)); +} + + +011001,3.RT,7.IMMEDIATE:MICROMIPS:16::LWGP +"lwgp r, (gp)" +*micromips32: +*micromips64: +{ + GPR[TRT] = EXTEND32 ( + do_load (SD_, AccessLength_WORD, GPR[28], IMM_SHIFT_2BIT)); +} + + +010010,5.RT,5.IMMEDIATE:MICROMIPS:16::LWSP +"lwsp r, (sp)" +*micromips32: +*micromips64: +{ + GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, SP, IMM_SHIFT_2BIT)); +} + + +010001,10000,5.RD:POOL16C:16::MFHI16 +"mfhi16 r" +*micromips32: +*micromips64: +{ + do_mfhi (SD_, RD); +} + + +010001,10010,5.RD:POOL16C:16::MFLO16 +"mflo16 r" +*micromips32: +*micromips64: +{ + do_mflo (SD_, RD); +} + + +000011,5.RD,5.RS:MICROMIPS:16::MOVE16 +"nop":RD==0&&RS==0 +"move16 r, r" +*micromips32: +*micromips64: +{ + GPR[RD] = GPR[RS]; +} + + +:%s::::DESTREGS:int regs +*micromips32: +*micromips64: +{ + switch (regs) + { + case 0: return "a1, a2,"; + case 1: return "a1, a3,"; + case 2: return "a2, a3,"; + case 3: return "a0, s5,"; + case 4: return "a0, s6,"; + case 5: return "a0, a1,"; + case 6: return "a0, a2,"; + case 7: return "a0, a3,"; + default: return ""; + } +} + +100001,3.DESTREGS,3.RT,3.RS,0:MICROMIPS:16::MOVEP +"movep %s r, r" +*micromips32: +*micromips64: +{ + int rd; + int re; + int dest = DESTREGS; + + if (dest == 0 || dest == 1) + rd = 5; + else if (dest == 2) + rd = 6; + else + rd = 4; + + if (dest == 0 || dest == 6) + re = 6; + else if (dest == 1 || dest == 2 || dest == 7) + re = 7; + else if (dest == 3) + re = 21; + else if (dest == 4) + re = 22; + /* assume dest is 5 */ + else + re = 5; + + GPR[rd] = GPR[ERS]; + GPR[re] = GPR[ERT]; +} + + +010001,0000,3.RT,3.RS:POOL16C:16::NOT16 +"not16 r, r" +*micromips32: +*micromips64: +{ + do_nor (SD_, 0, TRS, TRT); +} + + +010001,0011,3.RT,3.RS:POOL16C:16::OR16 +"or16 r, r" +*micromips32: +*micromips64: +{ + do_or (SD_, TRS, TRT, TRT); +} + + +100010,3.RT_S,3.BASE,4.IMMEDIATE:MICROMIPS:16::SB16 +"sb16 r, (r)" +*micromips32: +*micromips64: +{ + do_store (SD_, AccessLength_BYTE, GPR[TBASE], IMMEDIATE, GPR[TRT_S]); +} + + +010001,101100,4.CODE:POOL16C:16::SDBBP16 +"sdbbp16 %#lx" +*micromips32: +*micromips64: +{ + SignalException (DebugBreakPoint, instruction_0); +} + + +101010,3.RT_S,3.BASE,4.IMMEDIATE:MICROMIPS:16::SH16 +"sh16 r, (r)" +*micromips32: +*micromips64: +{ + do_store (SD_, AccessLength_HALFWORD, GPR[TBASE], IMM_SHIFT_1BIT, GPR[TRT_S]); +} + + +001001,3.RD,3.RT,3.SHIFT,0:POOL16B:16::SLL16 +"sll16 r, r, " +*micromips32: +*micromips64: +{ + do_sll (SD_, TRT, TRD, SHIFT_DEC); +} + + +001001,3.RD,3.RT,3.SHIFT,1:POOL16B:16::SRL16 +"srl16 r, r, " +*micromips32: +*micromips64: +{ + do_srl (SD_, TRT, TRD, SHIFT_DEC); +} + + +000001,3.RD,3.RT,3.RS,1:POOL16A:16::SUBU16 +"subu16 r, r, r" +*micromips32: +*micromips64: +{ + do_subu (SD_, TRS, TRT, TRD); +} + + +111010,3.RT_S,3.BASE,4.IMMEDIATE:MICROMIPS:16::SW16 +"sw16 r, (r)" +*micromips32: +*micromips64: +{ + do_store (SD_, AccessLength_WORD, GPR[TBASE], IMM_SHIFT_2BIT, GPR[TRT_S]); +} + + +110010,5.RT,5.IMMEDIATE:MICROMIPS:16::SWSP +"swsp r, (sp)" +*micromips32: +*micromips64: +{ + do_store (SD_, AccessLength_WORD, SP, IMM_SHIFT_2BIT, GPR[RT]); +} + + +010001,0101,2.LWMREGS,4.IMMEDIATE:POOL16C:16::SWM16 +"swm16 %s, (sp)" +*micromips32: +*micromips64: +{ + int address = GPR[SPIDX] + IMM_SHIFT_2BIT; + int reg_offset; + + for (reg_offset = 0; reg_offset <= LWMREGS; reg_offset++) + do_store (SD_, AccessLength_WORD, address, reg_offset * 4, + GPR[16 + reg_offset]); + + do_store (SD_, AccessLength_WORD, address, reg_offset * 4, RA); +} + + +010001,0001,3.RT,3.RS:POOL16C:16::XOR16 +"xor16 r, r" +*micromips32: +*micromips64: +{ + do_xor (SD_, TRS, TRT, TRT); +} + + +000000,5.RT,5.RS,5.RD,00100,010000:POOL32A:32::ADD +"add r, r, r" +*micromips32: +*micromips64: +{ + do_add (SD_, RS, RT, RD); +} + + +000100,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::ADDI +"addi r, r, " +*micromips32: +*micromips64: +{ + do_addi (SD_, RS, RT, IMMEDIATE); +} + + +001100,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::ADDIU +"li r, ":RS==0 +"addiu r, r, " +*micromips32: +*micromips64: +{ + do_addiu (SD_, RS, RT, IMMEDIATE); +} + + +011110,3.RS,23.IMMEDIATE:MICROMIPS:32::ADDIUPC +"addiupc r, " +*micromips32: +*micromips64: +{ + GPR[TRS] = EXTEND32 ((CIA & ~3) + EXTEND25 (IMM_SHIFT_2BIT)); +} + + +000000,5.RT,5.RS,5.RD,00101,010000:POOL32A:32::ADDU +"addu r, r, r" +*micromips32: +*micromips64: +{ + do_addu (SD_, RS, RT, RD); +} + + +000000,5.RT,5.RS,5.RD,01001,010000:POOL32A:32::AND +"and r, r, r" +*micromips32: +*micromips64: +{ + do_and (SD_, RS, RT, RD); +} + + +110100,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::ANDI +"andi r, r, " +*micromips32: +*micromips64: +{ + do_andi (SD_, RS, RT, IMMEDIATE); +} + + +010000,1110,1.TF,3.CC,00,16.IMMEDIATE:POOL32I:32,f::BC1a +"bc1%s ":CC == 0 +"bc1%s , " +*micromips32: +*micromips64: +{ + check_fpu (SD_); + if (GETFCC(CC) == TF) + { + address_word dest = NIA + (EXTEND16 (IMMEDIATE) << 1); + NIA = delayslot_micromips (SD_, dest, NIA, MICROMIPS_DELAYSLOT_SIZE_ANY); + } +} + + +010000,1010,1.TF,3.CC,00,16.IMMEDIATE:POOL32I:32::BC2a +"bc2%s , ":CC == 0 +"bc2%s , " +*micromips32: +*micromips64: + + +100101,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::BEQ +"b ":RT == 0 && RS == 0 +"beq r, r, " +*micromips32: +*micromips64: +{ + address_word offset = EXTEND16 (IMMEDIATE) << 1; + if ((signed_word) GPR[RS] == (signed_word) GPR[RT]) + NIA = delayslot_micromips (SD_, NIA + offset, NIA, + MICROMIPS_DELAYSLOT_SIZE_ANY); +} + +010000,00010,5.RS,16.IMMEDIATE:POOL32I:32::BGEZ +"bgez r, " +*micromips32: +*micromips64: +{ + address_word offset = EXTEND16 (IMMEDIATE) << 1; + if ((signed_word) GPR[RS] >= 0) + NIA = delayslot_micromips (SD_, NIA + offset, NIA, + MICROMIPS_DELAYSLOT_SIZE_ANY); +} + + +010000,00111,5.RS,16.IMMEDIATE:POOL32I:32::BEQZC +"beqzc r, " +*micromips32: +*micromips64: +{ + address_word offset = EXTEND16 (IMMEDIATE) << 1; + if (GPR[RS] == 0) + NIA = NIA + offset; +} + + +010000,00011,5.RS,16.IMMEDIATE:POOL32I:32::BGEZAL +"bal ":RS == 0 +"bgezal r, " +*micromips32: +*micromips64: +{ + address_word offset = EXTEND16 (IMMEDIATE) << 1; + if (RS == 31) + Unpredictable (); + RA = (NIA + MICROMIPS_DELAYSLOT_SIZE_32) | ISA_MODE_MICROMIPS; + if ((signed_word) GPR[RS] >= 0) + NIA = delayslot_micromips (SD_, NIA + offset, NIA, + MICROMIPS_DELAYSLOT_SIZE_32); +} + + +010000,00110,5.RS,16.IMMEDIATE:POOL32I:32::BGTZ +"bgtz r, " +*micromips32: +*micromips64: +{ + address_word offset = EXTEND16 (IMMEDIATE) << 1; + if ((signed_word) GPR[RS] > 0) + NIA = delayslot_micromips (SD_, NIA + offset, NIA, + MICROMIPS_DELAYSLOT_SIZE_ANY); +} + + +010000,10011,5.RS,16.IMMEDIATE:POOL32I:32::BGEZALS +"bal ":RS == 0 +"bgezals r, " +*micromips32: +*micromips64: +{ + address_word offset = EXTEND16 (IMMEDIATE) << 1; + if (RS == 31) + Unpredictable (); + RA = (NIA + MICROMIPS_DELAYSLOT_SIZE_16) | ISA_MODE_MICROMIPS; + if ((signed_word) GPR[RS] >= 0) + NIA = delayslot_micromips (SD_, NIA + offset, NIA, + MICROMIPS_DELAYSLOT_SIZE_16); +} + + +010000,00100,5.RS,16.IMMEDIATE:POOL32I:32::BLEZ +"blez r, " +*micromips32: +*micromips64: +{ + address_word offset = EXTEND16 (IMMEDIATE) << 1; + /* NOTE: The branch occurs AFTER the next instruction has been + executed */ + if ((signed_word) GPR[RS] <= 0) + NIA = delayslot_micromips (SD_, NIA + offset, NIA, + MICROMIPS_DELAYSLOT_SIZE_ANY); +} + + +010000,00000,5.RS,16.IMMEDIATE:POOL32I:32::BLTZ +"bltz r, " +*micromips32: +*micromips64: +{ + address_word offset = EXTEND16 (IMMEDIATE) << 1; + if ((signed_word) GPR[RS] < 0) + NIA = delayslot_micromips (SD_, NIA + offset, NIA, + MICROMIPS_DELAYSLOT_SIZE_ANY); +} + + +010000,00001,5.RS,16.IMMEDIATE:POOL32I:32::BLTZAL +"bltzal r, " +*micromips32: +*micromips64: +{ + address_word offset = EXTEND16 (IMMEDIATE) << 1; + if (RS == 31) + Unpredictable (); + RA = (NIA + MICROMIPS_DELAYSLOT_SIZE_32) | ISA_MODE_MICROMIPS; + /* NOTE: The branch occurs AFTER the next instruction has been + executed */ + if ((signed_word) GPR[RS] < 0) + NIA = delayslot_micromips (SD_, NIA + offset, NIA, + MICROMIPS_DELAYSLOT_SIZE_32); +} + +010000,10001,5.RS,16.IMMEDIATE:POOL32I:32::BLTZALS +"bltzals r, " +*micromips32: +*micromips64: +{ + address_word offset = EXTEND16 (IMMEDIATE) << 1; + if (RS == 31) + Unpredictable (); + RA = (NIA + MICROMIPS_DELAYSLOT_SIZE_16) | ISA_MODE_MICROMIPS; + if ((signed_word) GPR[RS] < 0) + NIA = delayslot_micromips (SD_, NIA + offset, NIA, + MICROMIPS_DELAYSLOT_SIZE_16); +} + + +101101,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::BNE +"bne r, r, " +*micromips32: +*micromips64: +{ + address_word offset = EXTEND16 (IMMEDIATE) << 1; + if ((signed_word) GPR[RS] != (signed_word) GPR[RT]) + NIA = delayslot_micromips (SD_, NIA + offset, NIA, + MICROMIPS_DELAYSLOT_SIZE_ANY); +} + + +010000,00101,5.RS,16.IMMEDIATE:POOL32I:32::BNEZC +"bnezc r, " +*micromips32: +*micromips64: +{ + address_word offset = EXTEND16 (IMMEDIATE) << 1; + if ((signed_word) GPR[RS] != 0) + NIA = NIA + offset; +} + + +000000,20.CODE,000111:POOL32A:32::BREAK +"break %#lx" +*micromips32: +*micromips64: +{ + do_break (SD_, instruction_0); +} + + +001000,5.OP,5.BASE,0110,12.IMMEDIATE:POOL32B:32::CACHE +"cache , (r)" +*micromips32: +*micromips64: +{ + address_word base = GPR[BASE]; + address_word offset = EXTEND12 (IMMEDIATE); + address_word vaddr = loadstore_ea (SD_, base, offset); + address_word paddr; + int uncached; + if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, + isTARGET, isREAL)) + CacheOp (OP, vaddr, paddr, instruction_0); +} + + +011000,5.OP,5.BASE,1010011,9.IMMEDIATE:POOL32C:32::CACHEE +"cachee , (r)" +*micromips32: +*micromips64: + + +010101,5.RT,5.FS,0001000000,111011:POOL32F:32,f::CFC1 +"cfc1 r, f" +*micromips32: +*micromips64: +{ + do_cfc1 (SD_, RT, FS); +} + + +000000,5.RT,5.IMPL,1100110100,111100:POOL32A:32::CFC2 +"cfc2 r, " +*micromips32: +*micromips64: + + +000000,5.RT,5.RS,0100101100,111100:POOL32A:32::CLO +"clo r, r" +*micromips32: +*micromips64: +{ + do_clo (SD_, RT, RS); +} + + +000000,5.RT,5.RS,0101101100,111100:POOL32A:32::CLZ +"clz r, r" +*micromips32: +*micromips64: +{ + do_clz (SD_, RT, RS); +} + + +000000,23.COFUN,010:POOL32A:32::COP2 +"cop2 " +*micromips32: +*micromips64: + + +010101,5.RT,5.FS,0001100000,111011:POOL32F:32,f::CTC1 +"ctc1 r, f" +*micromips32: +*micromips64: +{ + do_ctc1 (SD_, RT, FS); +} + + +000000,5.RT,5.IMPL,1101110100,111100:POOL32A:32::CTC2 +"ctc2 r, " +*micromips32: +*micromips64: + + +000000,00000000001110001101,111100:POOL32A:32::DERET +"deret" +*micromips32: +*micromips64: + + +000000,00000,5.RS,0100011101,111100:POOL32A:32::DI +"di":RS == 0 +"di r" +*micromips32: +*micromips64: +{ + do_di (SD_, RS); +} + +000000,5.RT,5.RS,1010101100,111100:POOL32A:32::DIV +"div r, r" +*micromips32: +*micromips64: +{ + do_div (SD_, RS, RT); +} + + +000000,5.RT,5.RS,1011101100,111100:POOL32A:32::DIVU +"divu r, r" +*micromips32: +*micromips64: +{ + do_divu (SD_, RS, RT); +} + + +000000,00000000000001100000,000000:POOL32A:32::EHB +"ehb" +*micromips32: +*micromips64: + + +000000,00000,5.RS,0101011101,111100:POOL32A:32::EI +"ei":RS == 0 +"ei r" +*micromips32: +*micromips64: +{ + do_ei (SD_, RS); +} + +000000,00000000001111001101,111100:POOL32A:32::ERET +"eret" +*micromips32: +*micromips64: +{ + if (SR & status_ERL) + { + /* Oops, not yet available */ + sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported"); + NIA = EPC; + SR &= ~status_ERL; + } + else + { + NIA = EPC; + SR &= ~status_EXL; + } +} + + +000000,5.RT,5.RS,5.MSBD,5.LSB,101100:POOL32A:32::EXT +"ext r, r, , " +*micromips32: +*micromips64: +{ + do_ext (SD_, RT, RS, LSB, MSBD); +} + + +000000,5.RT,5.RS,5.MSBD,5.LSB,001100:POOL32A:32::INS +"ins r, r, , " +*micromips32: +*micromips64: +{ + do_ins (SD_, RT, RS, LSB, MSBD); +} + + +110101,26.IMMEDIATE:MICROMIPS:32::J +"j " +*micromips32: +*micromips64: +{ + address_word region = (NIA & MASK (63, 27)); + NIA = delayslot_micromips (SD_, region | (IMM_SHIFT_1BIT), NIA, + MICROMIPS_DELAYSLOT_SIZE_ANY); +} + + +111101,26.IMMEDIATE:MICROMIPS:32::JAL +"jal " +*micromips32: +*micromips64: +{ + /* NOTE: The region used is that of the delay slot and NOT the + current instruction */ + address_word region = (NIA & MASK (63, 27)); + NIA = do_micromips_jal (SD_, (region | (IMM_SHIFT_1BIT)), NIA, + MICROMIPS_DELAYSLOT_SIZE_32); +} + + +011101,26.IMMEDIATE:MICROMIPS:32::JALS +"jals " +*micromips32: +*micromips64: +{ + address_word region = (NIA & MASK (63, 27)); + NIA = do_micromips_jal (SD_, (region | (IMM_SHIFT_1BIT)), NIA, + MICROMIPS_DELAYSLOT_SIZE_16); +} + +000000,5.RT!0,5.RS,0000111100,111100:POOL32A:32::JALR +"jalr r":RT == 31 +"jalr r, r" +*micromips32: +*micromips64: +{ + if (RS == RT) + Unpredictable (); + NIA = do_micromips_jalr (SD_, RT, RS, NIA, MICROMIPS_DELAYSLOT_SIZE_32); +} + +000000,5.RT,5.RS,0100111100,111100:POOL32A:32::JALRS +"jalrs r, r" +*micromips32: +*micromips64: +{ + if (RS == RT) + Unpredictable (); + NIA = do_micromips_jalr (SD_, RT, RS, NIA, MICROMIPS_DELAYSLOT_SIZE_16); +} + + +111100,26.IMMEDIATE:MICROMIPS:32::JALX +"jalx " +*micromips32: +*micromips64: +{ + address_word region = (NIA & MASK (63, 26)); + NIA = do_micromips_jal (SD_, (region | (IMM_SHIFT_2BIT)) | ISA_MODE_MIPS32, + NIA, MICROMIPS_DELAYSLOT_SIZE_32); + SD->isa_mode = ISA_MODE_MIPS32; +} + +000000,00000,5.RS,0000111100,111100:POOL32A:32::JR +"jr r" +*micromips32: +*micromips64: +{ + NIA = process_isa_mode (SD_, + delayslot_micromips (SD_, GPR[RS], NIA, + MICROMIPS_DELAYSLOT_SIZE_32)); +} + + +000000,5.RT,5.RS,0001111100,111100:POOL32A:32::JALR.HB +"jalr.hb r, r" +*micromips32: +*micromips64: +{ + if (RS == RT) + Unpredictable (); + NIA = do_micromips_jalr (SD_, RT, RS, NIA, MICROMIPS_DELAYSLOT_SIZE_32); +} + + +000000,5.RT,5.RS,0101111100,111100:POOL32A:32::JALRS.HB +"jalrs.hb r, r" +*micromips32: +*micromips64: +{ + if (RS == RT) + Unpredictable (); + NIA = do_micromips_jalr (SD_, RT, RS, NIA, MICROMIPS_DELAYSLOT_SIZE_16); +} + + +000000,00000,5.RS,0111111100,111100:POOL32A:32::JR.HB +"jr.hb r" +*micromips32: +*micromips64: +{ + NIA = process_isa_mode (SD_, + delayslot_micromips (SD_, GPR[RS], NIA, + MICROMIPS_DELAYSLOT_SIZE_32)); +} + + +000111,5.RT,5.BASE,16.IMMEDIATE:MICROMIPS:32::LB +"lb r, (r)" +*micromips32: +*micromips64: +{ + do_lb (SD_, RT, IMMEDIATE, BASE); +} + + +011000,5.RT,5.BASE,0110100,9.IMMEDIATE:POOL32C:32::LBE +"lbe r, (r)" +*micromips32: +*micromips64: + + +000101,5.RT,5.BASE,16.IMMEDIATE:MICROMIPS:32::LBU +"lbu r, (r)" +*micromips32: +*micromips64: +{ + do_lbu (SD_, RT, IMMEDIATE, BASE); +} + + +011000,5.RT,5.BASE,0110000,9.IMMEDIATE:POOL32C:32::LBUE +"lbue r, (r)" +*micromips32: +*micromips64: + + +101111,5.FT,5.BASE,16.IMMEDIATE:MICROMIPS:32,f::LDC1a +"ldc1 f, (r)" +*micromips32: +{ + check_fpu (SD_); + COP_LD (1, FT, do_load_double (SD_, GPR[BASE], EXTEND16 (IMMEDIATE))); +} + + +101111,5.FT,5.BASE,16.IMMEDIATE:MICROMIPS:32,f::LDC1b +"ldc1 f, (r)" +*micromips64: +{ + check_fpu (SD_); + COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], + EXTEND16 (IMMEDIATE))); +} + + +001000,5.RT,5.BASE,0010,12.IMMEDIATE:POOL32B:32::LDC2 +"ldc2 r, (r)" +*micromips32: +*micromips64: + + +001111,5.RT,5.BASE,16.IMMEDIATE:MICROMIPS:32::LH +"lh r, (r)" +*micromips32: +*micromips64: +{ + do_lh (SD_, RT, IMMEDIATE, BASE); +} + + +011000,5.RT,5.BASE,0110101,9.IMMEDIATE:POOL32C:32::LHE +"lhe r, (r)" +*micromips32: +*micromips64: + + +001101,5.RT,5.BASE,16.IMMEDIATE:MICROMIPS:32::LHU +"lhu r, (r)" +*micromips32: +*micromips64: +{ + do_lhu (SD_, RT, IMMEDIATE, BASE); +} + + +011000,5.RT,5.BASE,0110001,9.IMMEDIATE:POOL32C:32::LHUE +"lhue r, (r)" +*micromips32: +*micromips64: + + +011000,5.RT,5.BASE,0011,12.IMMEDIATE:POOL32C:32::LL +"ll r, (r)" +*micromips32: +*micromips64: +{ + do_ll (SD_, RT, EXTEND12 (IMMEDIATE), BASE); +} + + +011000,5.RT,5.BASE,0110110,9.IMMEDIATE:POOL32C:32::LLE +"lle r, (r)" +*micromips32: +*micromips64: + + +010000,01101,5.RS,16.IMMEDIATE:POOL32I:32::LUI +"lui r, " +*micromips32: +*micromips64: +{ + do_lui (SD_, RS, IMMEDIATE); +} + + +010101,5.INDEX,5.BASE,5.FD,00101,001000:POOL32F:32,f::LUXC1 +"luxc1 f, r(r)" +*micromips32: +{ + do_luxc1_32 (SD_, FD, INDEX, BASE); +} + + +010101,5.INDEX,5.BASE,5.FD,00101,001000:POOL32F:64,f::LUXC1 +"luxc1 f, r(r)" +*micromips64: +{ + check_fpu (SD_); + check_u64 (SD_, instruction_0); + do_luxc1_64 (SD_, FD, INDEX, BASE); +} + + +111111,5.RT,5.BASE,16.IMMEDIATE:MICROMIPS:32::LW +"lw r, (r)" +*micromips32: +*micromips64: +{ + do_lw (SD_, RT, IMMEDIATE, BASE); +} + + +100111,5.FT,5.BASE,16.IMMEDIATE:MICROMIPS:32,f::LWC1 +"lwc1 f, (r)" +*micromips32: +*micromips64: +{ + do_lwc1 (SD_, FT, IMMEDIATE, BASE); +} + + +001000,5.RT,5.BASE,0000,12.IMMEDIATE:POOL32B:32::LWC2 +"lwc2 r, (r)" +*micromips32: +*micromips64: + + +011000,5.RT,5.BASE,0110111,9.IMMEDIATE:POOL32C:32::LWE +"lwe r, (r)" +*micromips32: +*micromips64: + + +011000,5.RT,5.BASE,0110011,9.IMMEDIATE:POOL32C:32::LWEE +"lwee r, (r)" +*micromips32: +*micromips64: + + +011000,5.RT,5.BASE,0000,12.IMMEDIATE:POOL32C:32::LWL +"lwl r, (r)" +*micromips32: +*micromips64: +{ + do_lwl (SD_, RT, EXTEND12 (IMMEDIATE), BASE); +} + + +011000,5.RT,5.BASE,0110010,9.IMMEDIATE:POOL32C:32::LWLE +"lwle r, (r)" +*micromips32: +*micromips64: + +:%s::::LWM32REGS:int lwmregs +*micromips32: +*micromips64: +{ + if (lwmregs & 0x10) + { + switch(lwmregs & 0xf) + { + case 0: + return "ra"; + case 1: + return "s0, ra"; + case 2: + return "s0, s1, ra"; + case 3: + return "s0, s1, s2, ra"; + case 4: + return "s0, s1, s2, s3, ra"; + case 5: + return "s0, s1, s2, s3, s4, ra"; + case 6: + return "s0, s1, s2, s3, s4, s5, ra"; + case 7: + return "s0, s1, s2, s3, s4, s5, s6, ra"; + case 8: + return "s0, s1, s2, s3, s4, s5, s6, s7, ra"; + case 9: + return "s0, s1, s2, s3, s4, s5, s6, s7, s8, ra"; + default: + return ""; + } + } + else + { + switch(lwmregs & 0xf) + { + case 1: + return "s0"; + case 2: + return "s0, s1"; + case 3: + return "s0, s1, s2"; + case 4: + return "s0, s1, s2, s3"; + case 5: + return "s0, s1, s2, s3, s4"; + case 6: + return "s0, s1, s2, s3, s4, s5"; + case 7: + return "s0, s1, s2, s3, s4, s5, s6"; + case 8: + return "s0, s1, s2, s3, s4, s5, s6, s7"; + case 9: + return "s0, s1, s2, s3, s4, s5, s6, s7, s8"; + default: + return ""; + } + } +} + +001000,5.LWM32REGS,5.BASE,0101,12.IMMEDIATE:POOL32B:32::LWM32 +"lwm32 %s, (r)" +*micromips32: +*micromips64: +{ + int address_base = GPR[BASE] + EXTEND12 (IMMEDIATE); + int reg_offset; + for (reg_offset = 0; reg_offset < (LWM32REGS & 0xf); reg_offset++) + { + int dst = (reg_offset == 8) ? 30 : 16 + reg_offset; + GPR[dst] = EXTEND32 (do_load (SD_, AccessLength_WORD, address_base, + 4 * reg_offset)); + } + + if (LWM32REGS & 0x10) + RA = EXTEND32 (do_load (SD_, AccessLength_WORD, address_base, + 4 * reg_offset)); +} + + +001000,5.RD,5.BASE,0001,12.IMMEDIATE:POOL32B:32::LWP +"lwp r, (r)" +*micromips32: +*micromips64: +{ + if (BASE == RD || RD == 31) + Unpredictable (); + else + { + do_lw (SD_, RD, EXTEND12 (IMMEDIATE), BASE); + do_lw (SD_, RD + 1, EXTEND12 (IMMEDIATE) + 4, BASE); + } +} + + +011000,5.RT,5.BASE,0001,12.IMMEDIATE:POOL32C:32::LWR +"lwr r, (r)" +*micromips32: +*micromips64: +{ + do_lwr (SD_, RT, EXTEND12 (IMMEDIATE), BASE); +} + + +011000,5.RT,5.BASE,1110,12.IMMEDIATE:POOL32C:32::LWU +"lwu r, (r)" +*micromips32: +*micromips64: +{ + do_lwu (SD_, RT, IMMEDIATE, BASE, instruction_0); +} + + +010101,5.INDEX,5.BASE,5.FD,00001,001000:POOL32F:32,f::LWXC1 +"lwxc1 f, (r)" +*micromips32: +*micromips64: +{ + do_lwxc1 (SD_, FD, INDEX, BASE, instruction_0); +} + + +000000,5.INDEX,5.BASE,5.RD,00100,011000:POOL32A:32::LWXS +"lwxs r, r(r)" +*micromips32: +*micromips64: +{ + GPR[RD] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], + GPR[INDEX] * 4)); +} + + +000000,5.RT,5.RS,1100101100,111100:POOL32A:32::MADD +"madd r, r" +*micromips32: +*micromips64: +{ + do_madd (SD_, RS, RT); +} + + +000000,5.RT,5.RS,1101101100,111100:POOL32A:32::MADDU +"maddu r, r" +*micromips32: +*micromips64: +{ + do_maddu (SD_, RS, RT); +} + + +000000,5.RT,5.RS,00,3.SEL,00011,111100:POOL32A:32::MFC0 +"mfc0 r, r": SEL == 0 +"mfc0 r, r, " +*micromips32: +*micromips64: +{ + DecodeCoproc (instruction_0, 0, cp0_mfc0, RT, RS, SEL); +} + + +010101,5.RT,5.FS,0010000000,111011:POOL32F:32,f::MFC1 +"mfc1 r, f" +*micromips32: +*micromips64: +{ + do_mfc1b (SD_, RT, FS); +} + + +000000,5.RT,5.IMPL,0100110100,111100:POOL32A:32::MFC2 +"mfc2 r, " +*micromips32: +*micromips64: + + +010101,5.RT,5.FS,0011000000,111011:POOL32F:32,f::MFHC1 +"mfhc1 r, f" +*micromips32: +*micromips64: +{ + do_mfhc1 (SD_, RT, FS); +} + + +000000,5.RT,5.IMPL,1000110100,111100:POOL32A:32::MFHC2 +"mfhc2 r, " +*micromips32: +*micromips64: + + +000000,00000,5.RS,0000110101,111100:POOL32A:32::MFHI +"mfhi r" +*micromips32: +*micromips64: +{ + do_mfhi (SD_, RS); +} + + +000000,00000,5.RS,0001110101,111100:POOL32A:32::MFLO +"mflo r" +*micromips32: +*micromips64: +{ + do_mflo (SD_, RS); +} + + +// MOVF +// MOVT +010101,5.RT,5.RS,3.CC,0,1.TF,00101,111011:POOL32F:32::MOVtf +"mov%s r, r, CC" +*micromips32: +*micromips64: +{ + do_movtf (SD_, TF, RT, RS, CC); +} + + +000000,5.RT,5.RS,5.RD,00000,011000:POOL32A:32::MOVN +"movn r, r, r" +*micromips32: +*micromips64: +{ + do_movn (SD_, RD, RS, RT); +} + + +000000,5.RT,5.RS,5.RD,00001,011000:POOL32A:32::MOVZ +"movz r, r, r" +*micromips32: +*micromips64: +{ + do_movz (SD_, RD, RS, RT); +} + + +000000,5.RT,5.RS,1110101100,111100:POOL32A:32::MSUB +"msub r, r" +*micromips32: +*micromips64: +{ + do_msub (SD_, RS, RT); +} + + +000000,5.RT,5.RS,1111101100,111100:POOL32A:32::MSUBU +"msubu r, r" +*micromips32: +*micromips64: +{ + do_msubu (SD_, RS, RT); +} + + +000000,5.RT,5.RS,00,3.SEL,01011,111100:POOL32A:32::MTC0 +"mtc0 r, r": SEL == 0 +"mtc0 r, r, " +*micromips32: +*micromips64: +{ + DecodeCoproc (instruction_0, 0, cp0_mtc0, RT, RS, SEL); +} + + +010101,5.RT,5.FS,0010100000,111011:POOL32F:32,f::MTC1 +"mtc1 r, f" +*micromips32: +*micromips64: +{ + do_mtc1b (SD_, RT, FS); +} + + +000000,5.RT,5.IMPL,0101110100,111100:POOL32A:32::MTC2 +"mtc2 r, " +*micromips32: +*micromips64: + + +010101,5.RT,5.FS,0011100000,111011:POOL32F:32,f::MTHC1 +"mthc1 r, f" +*micromips32: +*micromips64: +{ + do_mthc1 (SD_, RT, FS); +} + + +000000,5.RT,5.IMPL,1001110100,111100:POOL32A:32::MTHC2 +"mthc2 r, " +*micromips32: +*micromips64: + + +000000,00000,5.RS,0010110101,111100:POOL32A:32::MTHI +"mthi r" +*micromips32: +*micromips64: +{ + do_mthi (SD_, RS); +} + + +000000,00000,5.RS,0011110101,111100:POOL32A:32::MTLO +"mtlo r" +*micromips32: +*micromips64: +{ + do_mtlo (SD_, RS); +} + + +000000,5.RT,5.RS,5.RD,01000,010000:POOL32A:32::MUL +"mul r, r, r" +*micromips32: +*micromips64: +{ + do_mul (SD_, RD, RS, RT); +} + + +000000,5.RT,5.RS,1000101100,111100:POOL32A:32::MULT +"mult r, r" +*micromips32: +*micromips64: +{ + do_mult (SD_, RS, RT, 0); +} + + +000000,5.RT,5.RS,1001101100,111100:POOL32A:32::MULTU +"multu r r" +*micromips32: +*micromips64: +{ + do_multu (SD_, RS, RT, 0); +} + + +000000,00000000000000000000,000000:POOL32A:32::NOP +"nop" +*micromips32: +*micromips64: +{ +} + + +000000,5.RT,5.RS,5.RD,01011,010000:POOL32A:32::NOR +"nor r, r, r" +*micromips32: +*micromips64: +{ + do_nor (SD_, RS, RT, RD); +} + + +000000,5.RT,5.RS,5.RD,01010,010000:POOL32A:32::OR +"or r, r, r" +*micromips32: +*micromips64: +{ + do_or (SD_, RS, RT, RD); +} + + +010100,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::ORI +"ori r, r, " +*micromips32: +*micromips64: +{ + do_ori (SD_, RS, RT, IMMEDIATE); +} + + +000000,00000000000010100000,000000:POOL32A:32::PAUSE +"pause" +*micromips32: +*micromips64: + + +011000,5.HINT,5.BASE,0010,12.IMMEDIATE:POOL32C:32::PREF +"pref , (r)" +*micromips32: +*micromips64: +{ + do_pref (SD_, HINT, EXTEND12 (IMMEDIATE), BASE); +} + + +011000,5.HINT,5.BASE,1010010,9.IMMEDIATE:POOL32C:32::PREFE +"prefe , (r)" +*micromips32: +*micromips64: + + +010101,5.INDEX,5.BASE,5.HINT,00110,100000:POOL32F:32::PREFX +"prefx , r(r)" +*micromips32: +*micromips64: +{ + do_prefx (SD_, HINT, INDEX, BASE); +} + +000000,5.RT,5.RS,0110101100,111100:POOL32A:32::RDHWR +"rdhwr r, r" +*micromips32: +*micromips64: +{ + do_rdhwr (SD_, RT, RS); +} + +000000,5.RT,5.RS,1110000101,111100:POOL32A:32::RDPGPR +"rdpgpr r, r" +*micromips32: +*micromips64: + + +000000,5.RT,5.RS,5.SHIFT,00011,000000:POOL32A:32::ROTR +"rotr r, r, " +*micromips32: +*micromips64: +{ + GPR[RT] = do_ror (SD_, GPR[RS], SHIFT); +} + + +000000,5.RT,5.RS,5.RD,00011,010000:POOL32A:32::ROTRV +"rotrv r, r, r" +*micromips32: +*micromips64: +{ + GPR[RD] = do_ror (SD_, GPR[RT], GPR[RS]); +} + + +000110,5.RT,5.BASE,16.IMMEDIATE:MICROMIPS:32::SB +"sb r, (r)" +*micromips32: +*micromips64: +{ + do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (IMMEDIATE), GPR[RT]); +} + + +011000,5.RT,5.BASE,1010101,9.IMMEDIATE:POOL32C:32::SBE +"sbe r, (r)" +*micromips32: +*micromips64: + + +011000,5.RT,5.BASE,1011,12.IMMEDIATE:POOL32C:32::SC +"sc r, (r)" +*micromips32: +*micromips64: +{ + do_sc (SD_, RT, EXTEND12 (IMMEDIATE), BASE, instruction_0); +} + + +011000,5.RT,5.BASE,1010110,9.IMMEDIATE:POOL32C:32::SCE +"sce r, (r)" +*micromips32: +*micromips64: + + +000000,10.CODE,1101101101,111100:POOL32A:32::SDBBP +"sdbbp %#lx" +*micromips32: +*micromips64: +{ + SignalException (DebugBreakPoint, instruction_0); +} + + +101110,5.FT,5.BASE,16.IMMEDIATE:MICROMIPS:32,f::SDC1a +"sdc1 f, (r)" +*micromips32: +{ + do_sdc1 (SD_, FT, IMMEDIATE, BASE); +} + + +101110,5.FT,5.BASE,16.IMMEDIATE:MICROMIPS:32,f::SDC1b +"sdc1 f, (r)" +*micromips64: +{ + check_fpu (SD_); + do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (IMMEDIATE), + COP_SD (1, FT)); +} + + +001000,5.RT,5.BASE,1010,12.IMMEDIATE:MICROMIPS:32::SDC2 +"sdc2 r, (r)" +*micromips32: +*micromips64: + + +000000,5.RT,5.RS,0010101100,111100:POOL32A:32::SEB +"seb r, r" +*micromips32: +*micromips64: +{ + do_seb (SD_, RT, RS); +} + + +000000,5.RT,5.RS,0011101100,111100:POOL32A:32::SEH +"seh r, r" +*micromips32: +*micromips64: +{ + do_seh (SD_, RT, RS); +} + + +001110,5.RT,5.BASE,16.IMMEDIATE:MICROMIPS:32::SH +"sh r, (r)" +*micromips32: +*micromips64: +{ + do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (IMMEDIATE), + GPR[RT]); +} + + +011000,5.RT,5.BASE,1010100,9.IMMEDIATE:POOL32C:32::SHE +"she r, (r)" +*micromips32: +*micromips64: + + +000000,5.RT!0,5.RS!0,5.SHIFT,00000,000000:POOL32A:32::SLL +"sll r, r, " +*micromips32: +*micromips64: +{ + do_sll (SD_, RS, RT, SHIFT); +} + + +000000,5.RT,5.RS,5.RD,00000,010000:POOL32A:32::SLLV +"sllv r, r, r" +*micromips32: +*micromips64: +{ + do_sllv (SD_, RS, RT, RD); +} + + +000000,5.RT,5.RS,5.RD,01101,010000:POOL32A:32::SLT +"slt r, r, r" +*micromips32: +*micromips64: +{ + do_slt (SD_, RS, RT, RD); +} + + +100100,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::SLTI +"slti r, r, " +*micromips32: +*micromips64: +{ + do_slti (SD_, RS, RT, IMMEDIATE); +} + + +101100,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::SLTIU +"sltiu r, r, " +*micromips32: +*micromips64: +{ + do_sltiu (SD_, RS, RT, IMMEDIATE); +} + + +000000,5.RT,5.RS,5.RD,01110,010000:POOL32A:32::SLTU +"sltu r, r, r" +*micromips32: +*micromips64: +{ + do_sltu (SD_, RS, RT, RD); +} + + +000000,5.RT,5.RS,5.SHIFT,00010,000000:POOL32A:32::SRA +"sra r, r, " +*micromips32: +*micromips64: +{ + do_sra (SD_, RS, RT, SHIFT); +} + + +000000,5.RT,5.RS,5.RD,00010,010000:POOL32A:32::SRAV +"srav r, r, r" +*micromips32: +*micromips64: +{ + do_srav (SD_, RS, RT, RD); +} + + +000000,5.RT,5.RS,5.SHIFT,00001,000000:POOL32A:32::SRL +"srl r, r, " +*micromips32: +*micromips64: +{ + do_srl (SD_, RS, RT, SHIFT); +} + + +000000,5.RT,5.RS,5.RD,00001,010000:POOL32A:32::SRLV +"srlv r, r, r" +*micromips32: +*micromips64: +{ + do_srlv (SD_, RS, RT, RD); +} + + +000000,00000000000000100000,000000:POOL32A:32::SSNOP +"ssnop" +*micromips32: +*micromips64: +{ +} + + +000000,5.RT,5.RS,5.RD,00110,010000:POOL32A:32::SUB +"sub r, r, r" +*micromips32: +*micromips64: +{ + do_sub (SD_, RD, RS, RT); +} + + +000000,5.RT,5.RS,5.RD,00111,010000:POOL32A:32::SUBU +"subu r, r, r" +*micromips32: +*micromips64: +{ + do_subu (SD_, RS, RT, RD); +} + + +010101,5.INDEX,5.BASE,5.FD,00110,001000:POOL32F:32,f::SUXC1 +"suxc1 f, r(r)" +*micromips32: +{ + do_suxc1_32 (SD_, FD, INDEX, BASE); +} + + +010101,5.INDEX,5.BASE,5.FD,00110,001000:POOL32F:64,f::SUXC1 +"suxc1 f, r(r)" +*micromips64: +{ + check_fpu (SD_); + check_u64 (SD_, instruction_0); + do_suxc1_64 (SD_, FD, INDEX, BASE); +} + +111110,5.RT,5.BASE,16.IMMEDIATE:MICROMIPS:32::SW +"sw r, (r)" +*micromips32: +*micromips64: +{ + do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (IMMEDIATE), GPR[RT]); +} + + +100110,5.FT,5.BASE,16.IMMEDIATE:MICROMIPS:32,f::SWC1 +"swc1 f, (r)" +*micromips32: +*micromips64: +{ + do_swc1 (SD_, FT, IMMEDIATE, BASE, instruction_0); +} + + +001000,5.RT,5.BASE,1000,12.IMMEDIATE:POOL32B:32::SWC2 +"swc2 r, (r)" +*micromips32: +*micromips64: + + +011000,5.RT,5.BASE,1010111,9.IMMEDIATE:POOL32C:32::SWE +"swe r, (r)" +*micromips32: +*micromips64: + + +011000,5.RT,5.BASE,1000,12.IMMEDIATE:POOL32C:32::SWL +"swl r, (r)" +*micromips32: +*micromips64: +{ + do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND12 (IMMEDIATE), + GPR[RT]); +} + + +011000,5.RT,5.BASE,1010000,9.IMMEDIATE:POOL32C:32::SWLE +"swle r, (r)" +*micromips32: +*micromips64: + + +001000,5.LWM32REGS,5.BASE,1101,12.IMMEDIATE:POOL32B:32::SWM32 +"swm32 %s, (r)" +*micromips32: +*micromips64: +{ + int address_base = GPR[BASE] + EXTEND12 (IMMEDIATE); + int reg_offset; + for (reg_offset = 0; reg_offset < (LWM32REGS & 0xf); reg_offset++) + { + int src = (reg_offset == 8) ? 30 : 16 + reg_offset; + do_store (SD_, AccessLength_WORD, address_base, 4 * reg_offset, + GPR[src]); + } + + if (LWM32REGS & 0x10) + do_store (SD_, AccessLength_WORD, address_base, 4 * reg_offset, RA); +} + + +001000,5.RS1,5.BASE,1001,12.IMMEDIATE:POOL32B:32::SWP +"swp r, (r)" +*micromips32: +*micromips64: +{ + if (RS1 == 31) + Unpredictable (); + else + { + do_sw (SD_, RS1, EXTEND12 (IMMEDIATE), BASE); + do_sw (SD_, RS1 + 1, EXTEND12 (IMMEDIATE) + 4, BASE); + } +} + + +011000,5.RT,5.BASE,1001,12.IMMEDIATE:POOL32C:32::SWR +"swr r, (r)" +*micromips32: +*micromips64: +{ + do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND12 (IMMEDIATE), + GPR[RT]); +} + + +011000,5.RT,5.BASE,1010001,9.IMMEDIATE:POOL32C:32::SWRE +"swre r, (r)" +*micromips32: +*micromips64: + + +010101,5.INDEX,5.BASE,5.FD,00010,001000:POOL32F:32,f::SWXC1 +"swxc1 f, r(r)" +*micromips32: +*micromips64: +{ + do_swxc1 (SD_, FD, INDEX, BASE, instruction_0); +} + + +000000,00000,5.STYPE,0110101101,111100:POOL32A:32::SYNC +"sync " +*micromips32: +*micromips64: +{ + SyncOperation (STYPE); +} + + +010000,10000,5.BASE,16.IMMEDIATE:POOL32I:32::SYNCI +"synci (r)" +*micromips32: +*micromips64: +{ +} + +000000,10.CODE,1000101101,111100:POOL32A:32::SYSCALL +"syscall %#lx" +*micromips32: +*micromips64: +{ + SignalException (SystemCall, instruction_0); +} + + +000000,5.RT,5.RS,4.CODE,000000,111100:POOL32A:32::TEQ +"teq r, r" +*micromips32: +*micromips64: +{ + do_teq (SD_, RS, RT, instruction_0); +} + + +010000,01110,5.RS,16.IMMEDIATE:POOL32I:32::TEQI +"teqi r, " +*micromips32: +*micromips64: +{ + do_teqi (SD_, RS, IMMEDIATE, instruction_0); +} + + +000000,5.RT,5.RS,4.CODE,001000,111100:POOL32A:32::TGE +"tge r, r" +*micromips32: +*micromips64: +{ + do_tge (SD_, RS, RT, instruction_0); +} + + +010000,01001,5.RS,16.IMMEDIATE:POOL32I:32::TGEI +"tgei r, " +*micromips32: +*micromips64: +{ + do_tgei (SD_, RS, IMMEDIATE, instruction_0); +} + + +010000,01011,5.RS,16.IMMEDIATE:POOL32I:32::TGEIU +"tgeiu r, " +*micromips32: +*micromips64: +{ + do_tgeiu (SD_, RS, IMMEDIATE, instruction_0); +} + + +000000,5.RT,5.RS,4.CODE,010000,111100:POOL32A:32::TGEU +"tgeu r, r" +*micromips32: +*micromips64: +{ + do_tgeu (SD_, RS, RT, instruction_0); +} + + +000000,00000000000000001101,111100:POOL32A:32::TLBP +"tlbp" +*micromips32: +*micromips64: + + +000000,00000000000001001101,111100:POOL32A:32::TLBR +"tlbr" +*micromips32: +*micromips64: + + +000000,00000000000010001101,111100:POOL32A:32::TLBWI +"tlbwi" +*micromips32: +*micromips64: + + +000000,00000000000011001101,111100:POOL32A:32::TLBWR +"tlbwr" +*micromips32: +*micromips64: + + +000000,5.RT,5.RS,4.CODE,100000,111100:POOL32A:32::TLT +"tlt r, r, %#lx" +*micromips32: +*micromips64: +{ + do_tlt (SD_, RS, RT, instruction_0); +} + + +010000,01000,5.RS,16.IMMEDIATE:POOL32I:32::TLTI +"tlti r, " +*micromips32: +*micromips64: +{ + do_tlti (SD_, RS, IMMEDIATE, instruction_0); +} + + +010000,01010,5.RS,16.IMMEDIATE:POOL32I:32::TLTIU +"tltiu r, " +*micromips32: +*micromips64: +{ + do_tltiu (SD_, RS, IMMEDIATE, instruction_0); +} + + +000000,5.RT,5.RS,4.CODE,101000,111100:POOL32A:32::TLTU +"tltu r, r" +*micromips32: +*micromips64: +{ + do_tltu (SD_, RS, RT, instruction_0); +} + + +000000,5.RT,5.RS,4.CODE,110000,111100:POOL32A:32::TNE +"tne r, r" +*micromips32: +*micromips64: +{ + do_tne (SD_, RS, RT, instruction_0); +} + + +010000,01100,5.RS,16.IMMEDIATE:POOL32I:32::TNEI +"tnei r, " +*micromips32: +*micromips64: +{ + do_tnei (SD_, RS, IMMEDIATE, instruction_0); +} + + +000000,10.CODE,1001001101,111100:POOL32A:32::WAIT +"wait" +*micromips32: +*micromips64: + + +000000,5.RT,5.RS,1111000101,111100:POOL32A:32::WRPGPR +"wrpgpr r, r" +*micromips32: +*micromips64: + + +000000,5.RT,5.RS,0111101100,111100:POOL32A:32::WSBH +"wsbh r, r" +*micromips32: +*micromips64: +{ + do_wsbh (SD_, RT, RS); +} + + +000000,5.RT,5.RS,5.RD,01100,010000:POOL32A:32::XOR +"xor r, r, r" +*micromips32: +*micromips64: +{ + do_xor (SD_, RS, RT, RD); +} + + +011100,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::XORI +"xori r, r, " +*micromips32: +*micromips64: +{ + do_xori (SD_, RS, RT, IMMEDIATE); +} + + +:%s::::FMT_MICROMIPS:int fmt +{ + switch (fmt) + { + case 0: return "s"; + case 1: return "d"; + case 2: return "ps"; + default: return "?"; + } +} + + +:%s::::FMT_MICROMIPS_CVT_D:int fmt +{ + switch (fmt) + { + case 0: return "s"; + case 1: return "w"; + case 2: return "l"; + default: return "?"; + } +} + + +:%s::::FMT_MICROMIPS_CVT_S:int fmt +{ + switch (fmt) + { + case 0: return "d"; + case 1: return "w"; + case 2: return "l"; + default: return "?"; + } +} + + +010101,5.FT,5.FS,0,2.FMT_MICROMIPS!3,0001101,111011:POOL32F:32,f::ABS.fmt +"abs.%s f, f" +*micromips32: +*micromips64: +{ + do_abs_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FT, FS, + instruction_0); +} + + +010101,5.FT,5.FS,5.FD,0,2.FMT_MICROMIPS!3,00,110000:POOL32F:32,f::ADD.fmt +"add.%s f, f, f" +*micromips32: +*micromips64: +{ + do_add_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FS, FT, + instruction_0); +} + + +010101,5.FT,5.FS,5.FD,5.RS,011001:POOL32F:32,f::ALNV.PS +"alnv.ps f, f, f, r" +*micromips32: +*micromips64: +{ + do_alnv_ps (SD_, FD, FS, FT, RS, instruction_0); +} + + +010101,5.FT,5.FS,3.CC,0,2.FMT_MICROMIPS!3,4.COND,111100:POOL32F:32,f::C.cond.fmt +"c.%s.%s f, f":CC == 0 +"c.%s.%s , f, f" +*micromips32: +*micromips64: +{ + do_c_cond_fmt (SD_, COND, convert_fmt_micromips (SD_, FMT_MICROMIPS), CC, + FS, FT, instruction_0); +} + + +010101,5.FT,5.FS,0,1.FMT_MICROMIPS,01001100,111011:POOL32F:32,f::CEIL.L.fmt +"ceil.l.%s f, f" +*micromips32: +*micromips64: +{ + do_ceil_fmt (SD_, fmt_long, FMT_MICROMIPS, FT, FS, instruction_0); +} + + +010101,5.FT,5.FS,0,1.FMT_MICROMIPS,01101100,111011:POOL32F:32,f::CEIL.W.fmt +"ceil.w.%s f, f" +*micromips32: +*micromips64: +{ + do_ceil_fmt (SD_, fmt_word, FMT_MICROMIPS, FT, FS, instruction_0); +} + + +010101,5.FT,5.FS,0,2.FMT_MICROMIPS_CVT_D!3,1001101,111011:POOL32F:32,f::CVT.D.fmt +"cvt.d.%s f, f" +*micromips32: +*micromips64: +{ + do_cvt_d_fmt (SD_, convert_fmt_micromips_cvt_d (SD_, FMT_MICROMIPS_CVT_D), + FT, FS, instruction_0); +} + + +010101,5.FT,5.FS,0,1.FMT_MICROMIPS,00000100,111011:POOL32F:32,f::CVT.L.fmt +"cvt.l.%s f, f" +*micromips32: +*micromips64: +{ + do_cvt_l_fmt (SD_, FMT_MICROMIPS, FT, FS, instruction_0); +} + + +010101,5.FT,5.FS,5.FD,00110,000000:POOL32F:32,f::CVT.PS.S +"cvt.ps.s f, f, f" +*micromips32: +*micromips64: +{ + do_cvt_ps_s (SD_, FD, FS, FT, instruction_0); +} + + +010101,5.FT,5.FS,0,2.FMT_MICROMIPS_CVT_S!3,1101101,111011:POOL32F:32,f::CVT.S.fmt +"cvt.s.%s f, f" +*micromips32: +*micromips64: +{ + do_cvt_s_fmt (SD_, convert_fmt_micromips_cvt_s (SD_, FMT_MICROMIPS_CVT_S), + FT, FS, instruction_0); +} + + +010101,5.FT,5.FS,00,10000100,111011:POOL32F:32,f::CVT.S.PL +"cvt.s.pl f, f" +*micromips32: +*micromips64: +{ + do_cvt_s_pl (SD_, FT, FS, instruction_0); +} + + +010101,5.FT,5.FS,00,10100100,111011:POOL32F:32,f::CVT.S.PU +"cvt.s.pu f, f" +*micromips32: +*micromips64: +{ + do_cvt_s_pu (SD_, FT, FS, instruction_0); +} + + +010101,5.FT,5.FS,0,1.FMT_MICROMIPS,00100100,111011:POOL32F:32,f::CVT.W.fmt +"cvt.w.%s f, f" +*micromips32: +*micromips64: +{ + do_cvt_w_fmt (SD_, FMT_MICROMIPS, FT, FS, instruction_0); +} + + +010101,5.FT,5.FS,5.FD,0,2.FMT_MICROMIPS!2!3,11,110000:POOL32F:32,f::DIV.fmt +"div.%s f, f, f" +*micromips32: +*micromips64: +{ + do_div_fmt (SD_, FMT_MICROMIPS, FD, FS, FT, instruction_0); +} + + +010101,5.FT,5.FS,0,1.FMT_MICROMIPS,00001100,111011:POOL32F:32,f::FLOOR.L.fmt +"floor.l.%s f, f" +*micromips32: +*micromips64: +{ + do_floor_fmt (SD_, fmt_long, FMT_MICROMIPS, FT, FS); +} + + +010101,5.FT,5.FS,0,1.FMT_MICROMIPS,00101100,111011:POOL32F:32,f::FLOOR.W.fmt +"floor.w.%s f, f" +*micromips32: +*micromips64: +{ + do_floor_fmt (SD_, fmt_word, FMT_MICROMIPS, FT, FS); +} + + +010101,5.FT,5.FS,5.FD,5.FR,0,2.FMT_MICROMIPS!3,001:POOL32F:32,f::MADD.fmt +"madd.%s f, f, f, f" +*micromips32: +*micromips64: +{ + do_madd_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FR, FS, + FT, instruction_0); +} + +010101,5.FT,5.FS,0,2.FMT_MICROMIPS!3,0000001,111011:POOL32F:32,f::MOV.fmt +"mov.%s f, f" +*micromips32: +*micromips64: +{ + do_mov_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FT, FS, + instruction_0); +} + + +010101,5.FT,5.FS,3.CC,00,2.FMT_MICROMIPS!3,00,1.TF,100000:POOL32F:32,f::MOVtf.fmt +"mov%s.%s f, f, " +*micromips32: +*micromips64: +{ + do_movtf_fmt (SD_, TF, convert_fmt_micromips (SD_, FMT_MICROMIPS), FT, + FS, CC); +} + + +010101,5.FT,5.FS,5.FD,0,2.FMT_MICROMIPS!3,00,111000:POOL32F:32,f::MOVN.fmt +"movn.%s f, f, r" +*micromips32: +*micromips64: +{ + do_movn_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FS, FT); +} + +010101,5.FT,5.FS,5.FD,0,2.FMT_MICROMIPS!3,01,111000:POOL32F:32,f::MOVZ.fmt +"movz.%s f, f, r" +*micromips32: +*micromips64: +{ + do_movz_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FS, FT); +} + + +010101,5.FT,5.FS,5.FD,5.FR,1,2.FMT_MICROMIPS!3,001:POOL32F:32,f::MSUB.fmt +"msub.%s f, f, f, f" +*micromips32: +*micromips64: +{ + do_msub_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FR, FS, + FT, instruction_0); +} + +010101,5.FT,5.FS,5.FD,0,2.FMT_MICROMIPS!3,10,110000:POOL32F:32,f::MUL.fmt +"mul.%s f, f, f" +*micromips32: +*micromips64: +{ + do_mul_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FS, FT, + instruction_0); +} + + +010101,5.FT,5.FS,0,2.FMT_MICROMIPS!3,0101101,111011:POOL32F:32,f::NEG.fmt +"neg.%s f, f" +*micromips32: +*micromips64: +{ + do_neg_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FT, FS, + instruction_0); +} + + +010101,5.FT,5.FS,5.FD,5.FR,0,2.FMT_MICROMIPS!3,010:POOL32F:32,f::NMADD.fmt +"nmadd.%s f, f, f, f" +*micromips32: +*micromips64: +{ + do_nmadd_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FR, FS, + FT, instruction_0); +} + +010101,5.FT,5.FS,5.FD,5.FR,1,2.FMT_MICROMIPS!3,010:POOL32F:32,f::NMSUB.fmt +"nmsub.%s f, f, f, f" +*micromips32: +*micromips64: +{ + do_nmsub_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FR, FS, + FT, instruction_0); +} + + +010101,5.FT,5.FS,5.FD,00010,000000:POOL32F:32,f::PLL.PS +"pll.ps f, f, f" +*micromips32: +*micromips64: +{ + do_pll_ps (SD_, FD, FS, FT, instruction_0); +} + + +010101,5.FT,5.FS,5.FD,00011,000000:POOL32F:32,f::PLU.PS +"plu.ps f, f, f" +*micromips32: +*micromips64: +{ + do_plu_ps (SD_, FD, FS, FT, instruction_0); +} + + +010101,5.FT,5.FS,5.FD,00100,000000:POOL32F:32,f::PUL.PS +"pul.ps f, f, f" +*micromips32: +*micromips64: +{ + do_pul_ps (SD_, FD, FS, FT, instruction_0); +} + + +010101,5.FT,5.FS,5.FD,00101,000000:POOL32F:32,f::PUU.PS +"puu.ps f, f, f" +*micromips32: +*micromips64: +{ + do_puu_ps (SD_, FD, FS, FT, instruction_0); +} + + +010101,5.FT,5.FS,0,1.FMT_MICROMIPS,01001000,111011:POOL32F:32,f::RECIP.fmt +"recip.%s f, f" +*micromips32: +*micromips64: +{ + do_recip_fmt (SD_, FMT_MICROMIPS, FT, FS); +} + + +010101,5.FT,5.FS,0,1.FMT_MICROMIPS,11001100,111011:POOL32F:32,f::ROUND.L.fmt +"round.l.%s f, f" +*micromips32: +*micromips64: +{ + do_round_fmt (SD_, fmt_long, FMT_MICROMIPS, FT, FS); +} + + +010101,5.FT,5.FS,0,1.FMT_MICROMIPS,11101100,111011:POOL32F:32,f::ROUND.W.fmt +"round.w.%s f, f" +*micromips32: +*micromips64: +{ + do_round_fmt (SD_, fmt_word, FMT_MICROMIPS, FT, FS); +} + + +010101,5.FT,5.FS,0,1.FMT_MICROMIPS,00001000,111011:POOL32F:32,f::RSQRT.fmt +"rsqrt.%s f, f" +*micromips32: +*micromips64: +{ + do_rsqrt_fmt (SD_, FMT_MICROMIPS, FT, FS); +} + + +010101,5.FT,5.FS,0,1.FMT_MICROMIPS,00101000,111011:POOL32F:32,f::SQRT.fmt +"sqrt.%s f, f" +*micromips32: +*micromips64: +{ + do_sqrt_fmt (SD_, FMT_MICROMIPS, FT, FS); +} + + +010101,5.FT,5.FS,5.FD,0,2.FMT_MICROMIPS!3,01,110000:POOL32F:32,f::SUB.fmt +"sub.%s f, f, f" +*micromips32: +*micromips64: +{ + do_sub_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FS, FT, + instruction_0); +} + + +010101,5.FT,5.FS,0,1.FMT_MICROMIPS,10001100,111011:POOL32F:32,f::TRUNC.L.fmt +"trunc.l.%s f, f" +*micromips32: +*micromips64: +{ + do_trunc_fmt (SD_, fmt_long, FMT_MICROMIPS, FT, FS); +} + + +010101,5.FT,5.FS,0,1.FMT_MICROMIPS,10101100,111011:POOL32F:32,f::TRUNC.W.fmt +"trunc.w.%s f, f" +*micromips32: +*micromips64: +{ + do_trunc_fmt (SD_, fmt_word, FMT_MICROMIPS, FT, FS); +} + +001000,5.LWM32REGS,5.BASE,0111,12.OFFSET:POOL32B:64::LDM +"ldm %s, (r)" +*micromips64: +{ + int address_base = GPR[BASE] + EXTEND12 (OFFSET); + int reg_offset; + for (reg_offset = 0; reg_offset < (LWM32REGS & 0xf); reg_offset++) + { + int dst = (reg_offset == 8) ? 30 : 16 + reg_offset; + GPR[dst] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, address_base, + 8 * reg_offset)); + } + + if (LWM32REGS & 0x10) + RA = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, address_base, + 8 * reg_offset)); +} + +001000,5.RD,5.BASE,0100,12.OFFSET:POOL32B:64::LDP +"ldp r, (r)" +*micromips64: +{ + if (BASE == RD || RD == 31) + Unpredictable (); + else + { + check_u64 (SD_, instruction_0); + GPR[RD] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], + EXTEND12 (OFFSET))); + GPR[RD + 1] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], + EXTEND12 (OFFSET) + 8)); + } +} + +001000,5.LWM32REGS,5.BASE,1111,12.OFFSET:POOL32B:64::SDM +"sdm %s, (r)" +*micromips64: +{ + int address_base = GPR[BASE] + EXTEND12 (OFFSET); + int reg_offset; + for (reg_offset = 0; reg_offset < (LWM32REGS & 0xf); reg_offset++) + { + int src = (reg_offset == 8) ? 30 : 16 + reg_offset; + do_store (SD_, AccessLength_DOUBLEWORD, address_base, 8 * reg_offset, + GPR[src]); + } + + if (LWM32REGS & 0x10) + do_store (SD_, AccessLength_DOUBLEWORD, address_base, 8 * reg_offset, RA); +} + +001000,5.RD,5.BASE,1100,12.OFFSET:POOL32B:64::SDP +"sdp r, (r)" +*micromips64: +{ + if (RD == 31) + Unpredictable (); + else + { + check_u64 (SD_, instruction_0); + do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND12 (OFFSET), + GPR[RD]); + do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND12 (OFFSET) + 8, + GPR[RD + 1]); + } +} + +010110,5.RT,5.RS,5.RD,00,100010000:POOL32S:64::DADD +"dadd r, r, r" +*micromips64: +{ + check_u64 (SD_, instruction_0); + do_dadd (SD_, RD, RS, RT); +} + +010110,5.RT,5.RS,10.IMMEDIATE,011100:POOL32S:64::DADDI +"daddi r, r, " +*micromips64: +{ + check_u64 (SD_, instruction_0); + do_daddi (SD_, RT, RS, IMMEDIATE); +} + +010111,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:64::DADDIU +"daddiu r, r, " +*micromips64: +{ + check_u64 (SD_, instruction_0); + do_daddiu (SD_, RS, RT, IMMEDIATE); +} + +010110,5.RT,5.RS,5.RD,00,101010000:POOL32S:64::DADDU +"daddu r, r, r" +*micromips64: +{ + check_u64 (SD_, instruction_0); + do_daddu (SD_, RS, RT, RD); +} + +010110,5.RT,5.RS,0100101100,111100:POOL32S:64::DCLO +"dclo r, r" +*micromips64: +{ + check_u64 (SD_, instruction_0); + do_dclo (SD_, RT, RS); +} + +010110,5.RT,5.RS,0101101100,111100:POOL32S:64::DCLZ +"dclz r, r" +*micromips64: +{ + check_u64 (SD_, instruction_0); + do_dclz (SD_, RT, RS); +} + +010110,5.RT,5.RS,1010101100,111100:POOL32S:64::DDIV +"ddiv r, r" +*micromips64: +{ + check_u64 (SD_, instruction_0); + do_ddiv (SD_, RS, RT); +} + +010110,5.RT,5.RS,1011101100,111100:POOL32S:64::DDIVU +"ddivu r, r" +*micromips64: +{ + check_u64 (SD_, instruction_0); + do_ddivu (SD_, RS, RT); +} + +010110,5.RT,5.RS,5.SIZE,5.LSB,101100:POOL32S:64::DEXT +"dext r, r, , " +*micromips64: +{ + check_u64 (SD_, instruction_0); + do_dext (SD_, RT, RS, LSB, SIZE); +} + +010110,5.RT,5.RS,5.SIZE,5.LSB,100100:POOL32S:64::DEXTM +"dextm r, r, , " +*micromips64: +{ + check_u64 (SD_, instruction_0); + do_dextm (SD_, RT, RS, LSB, SIZE); +} + +010110,5.RT,5.RS,5.SIZE,5.LSB,010100:POOL32S:64::DEXTU +"dextu r, r, , " +*micromips64: +{ + check_u64 (SD_, instruction_0); + do_dextu (SD_, RT, RS, LSB, SIZE); +} + +010110,5.RT,5.RS,5.MSB,5.LSB,001100:POOL32S:64::DINS +"dins r, r, , " +*micromips64: +{ + check_u64 (SD_, instruction_0); + do_dins (SD_, RT, RS, LSB, MSB); +} + +010110,5.RT,5.RS,5.MSB,5.LSB,000100:POOL32S:64::DINSM +"dinsm r, r, , " +*micromips64: +{ + check_u64 (SD_, instruction_0); + do_dinsm (SD_, RT, RS, LSB, MSB); +} + +010110,5.RT,5.RS,5.MSB,5.LSB,110100:POOL32S:64::DINSU +"dinsu r, r, , " +*micromips64: +{ + check_u64 (SD_, instruction_0); + do_dinsu (SD_, RT, RS, LSB, MSB); +} + +010110,5.RT,5.RS,00,3.SEL,00011,111100:POOL32S:64::DMFC0 +"dmfc0 r, r": SEL == 0 +"dmfc0 r, r, " +*micromips64: +{ + check_u64 (SD_, instruction_0); + DecodeCoproc (instruction_0, 0, cp0_dmfc0, RT, RS, SEL); +} + +010101,5.RT,5.FS,00,10010000,111011:POOL32F:64::DMFC1 +"dmfc1 r, f" +*micromips64: +{ + check_fpu (SD_); + check_u64 (SD_, instruction_0); + do_dmfc1b (SD_, RT, FS); +} + +010110,5.RT,5.RS,00,3.SEL,01011,111100:POOL32S:64::DMTC0 +"dmtc0 r, r": SEL == 0 +"dmtc0 r, r, " +*micromips64: +{ + check_u64 (SD_, instruction_0); + DecodeCoproc (instruction_0, 0, cp0_dmtc0, RT, RS, SEL); +} + +010101,5.RT,5.FS,00,10110000,111011:POOL32F:64::DMTC1 +"dmtc1 r, f" +*micromips64: +{ + check_fpu (SD_); + check_u64 (SD_, instruction_0); + do_dmtc1b (SD_, RT, FS); +} + +010110,5.RT,5.RS,1000101100,111100:POOL32S:64::DMULT +"dmult r, r" +*micromips64: +{ + check_u64 (SD_, instruction_0); + do_dmult (SD_, RS, RT, 0); +} + +010110,5.RT,5.RS,1001101100,111100:POOL32S:64::DMULTU +"dmultu r, r" +*micromips64: +{ + check_u64 (SD_, instruction_0); + do_dmultu (SD_, RS, RT, 0); +} + +010110,5.RT,5.RS,5.SA,00,011000000:POOL32S:64::DROTR +"drotr r, r, " +*micromips64: +{ + check_u64 (SD_, instruction_0); + GPR[RT] = do_dror (SD_, GPR[RS], SA); +} + +010110,5.RT,5.RS,5.SA,00,011001000:POOL32S:64::DROTR32 +"drotr32 r, r, " +*micromips64: +{ + check_u64 (SD_, instruction_0); + GPR[RT] = do_dror (SD_, GPR[RS], SA + 32); +} + +010110,5.RT,5.RS,5.RD,00,011010000:POOL32S:64::DROTRV +"drotrv r, r, r" +*micromips64: +{ + check_u64 (SD_, instruction_0); + GPR[RD] = do_dror (SD_, GPR[RT], GPR[RS]); +} + +010110,5.RT,5.RS,0111101100,111100:POOL32S:64::DSBH +"dsbh r, r" +*micromips64: +{ + check_u64 (SD_, instruction_0); + do_dsbh (SD_, RT, RS); +} + +010110,5.RT,5.RS,1111101100,111100:POOL32S:64::DSHD +"dshd r, r" +*micromips64: +{ + check_u64 (SD_, instruction_0); + do_dshd (SD_, RS, RT); +} + +010110,5.RT,5.RS,5.SA,00,000000000:POOL32S:64::DSLL +"dsll r, r, " +*micromips64: +{ + check_u64 (SD_, instruction_0); + do_dsll (SD_, RS, RT, SA); +} + +010110,5.RT,5.RS,5.SA,00,000001000:POOL32S:64::DSLL32 +"dsll32 r, r, " +*micromips64: +{ + check_u64 (SD_, instruction_0); + do_dsll32 (SD_, RT, RS, SA); +} + +010110,5.RT,5.RS,5.RD,00,000010000:POOL32S:64::DSLLV +"dsllv r, r, r" +*micromips64: +{ + check_u64 (SD_, instruction_0); + do_dsllv (SD_, RS, RT, RD); +} + +010110,5.RT,5.RS,5.SA,00,010000000:POOL32S:64::DSRA +"dsra r, r, " +*micromips64: +{ + check_u64 (SD_, instruction_0); + do_dsra (SD_, RS, RT, SA); +} + +010110,5.RT,5.RS,5.SA,00,010001000:POOL32S:64::DSRA32 +"dsra32 r, r, " +*micromips64: +{ + check_u64 (SD_, instruction_0); + do_dsra32 (SD_, RT, RS, SA); +} + +010110,5.RT,5.RS,5.RD,00,010010000:POOL32S:64::DSRAV +"dsrav r, r, r" +*micromips64: +{ + check_u64 (SD_, instruction_0); + do_dsrav (SD_, RS, RT, RD); +} + +010110,5.RT,5.RS,5.SA,00,001000000:POOL32S:64::DSRL +"dsrl r, r, " +*micromips64: +{ + check_u64 (SD_, instruction_0); + do_dsrl (SD_, RS, RT, SA); +} + +010110,5.RT,5.RS,5.SA,00,001001000:POOL32S:64::DSRL32 +"dsrl32 r, r, " +*micromips64: +{ + check_u64 (SD_, instruction_0); + do_dsrl32 (SD_, RT, RS, SA); +} + +010110,5.RT,5.RS,5.RD,00,001010000:POOL32S:64::DSRLV +"dsrlv r, r, r" +*micromips64: +{ + check_u64 (SD_, instruction_0); + do_dsrlv (SD_, RS, RT, RD); +} + +010110,5.RT,5.RS,5.RD,00,110001000:POOL32S:64::DSUB +"dsub r, r, r" +*micromips64: +{ + check_u64 (SD_, instruction_0); + do_dsub (SD_, RD, RS, RT); +} + +010110,5.RT,5.RS,5.RD,00,111001000:POOL32S:64::DSUBU +"dsubu r, r, r" +*micromips64: +{ + check_u64 (SD_, instruction_0); + do_dsubu (SD_, RS, RT, RD); +} + +110111,5.RT,5.BASE,16.OFFSET:MICROMIPS64:64::LD +"ld r, (r)" +*micromips64: +{ + check_u64 (SD_, instruction_0); + GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], + EXTEND16 (OFFSET))); +} + +011000,5.RT,5.BASE,0100,12.OFFSET:POOL32C:64::LDL +"ldl r, (r)" +*micromips64: +{ + check_u64 (SD_, instruction_0); + GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], + EXTEND12 (OFFSET), GPR[RT]); +} + +011000,5.RT,5.BASE,0101,12.OFFSET:POOL32C:64::LDR +"ldr r, (r)" +*micromips64: +{ + check_u64 (SD_, instruction_0); + GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], + EXTEND12 (OFFSET), GPR[RT]); +} + +010101,5.INDEX,5.BASE,5.FD,00,011001000:POOL32F:64,f::LDXC1 +"ldxc1 f, r(r)" +*micromips64: +{ + check_fpu (SD_); + check_u64 (SD_, instruction_0); + COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX])); +} + +011000,5.RT,5.BASE,0111,12.OFFSET:POOL32C:64::LLD +"lld r, (r)" +*micromips64: +{ + check_u64 (SD_, instruction_0); + do_lld (SD_, RT, OFFSET, BASE); +} + +011000,5.RT,5.BASE,1111,12.OFFSET:POOL32C:64::SCD +"scd r, (r)" +*micromips64: +{ + check_u64 (SD_, instruction_0); + do_scd (SD_, RT, OFFSET, BASE); +} + +110110,5.RT,5.BASE,16.OFFSET:MICROMIPS64:64::SD +"sd r, (r)" +*micromips64: +{ + check_u64 (SD_, instruction_0); + do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), + GPR[RT]); +} + +011000,5.RT,5.BASE,1100,12.OFFSET:POOL32C:64::SDL +"sdl r, (r)" +*micromips64: +{ + check_u64 (SD_, instruction_0); + do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND12 (OFFSET), + GPR[RT]); +} + +011000,5.RT,5.BASE,1101,12.OFFSET:POOL32C:64::SDR +"sdr r, (r)" +*micromips64: +{ + check_u64 (SD_, instruction_0); + do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND12 (OFFSET), + GPR[RT]); +} + +010101,5.INDEX,5.BASE,5.FD,00,100001000:POOL32F:64,f::SDXC1 +"sdxc1 f, r(r)" +*micromips64: +{ + check_fpu (SD_); + check_u64 (SD_, instruction_0); + do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], + COP_SD (1, FD)); +} -- cgit v1.1