From 369fba30897458a842d6f599fde08b45804ebef3 Mon Sep 17 00:00:00 2001 From: Doug Evans Date: Tue, 20 Jan 1998 06:17:32 +0000 Subject: * arch.c, arch.h, cpuall.h: New files. * arch-defs.h: Deleted. * mloop.in: Renamed from mainloop.in. * sem.c: Renamed from semantics.c. * Makefile.in: Update. * sem-ops.h: Deleted. * mem-ops.h: Deleted. start-sanitize-cygnus Add cgen support for generating files. end-sanitize-cygnus (arch): Renamed from CPU. * decode.c: Redone. * decode.h: Redone. * extract.c: Redone. * model.c: Redone. * sem-switch.c: Redone. * sem.c: Renamed from semantics.c, and redone. * m32r-sim.h (PROFILE_COUNT_FILLNOPS): Update. (GETTWI,SETTWI,BRANCH_NEW_PC): Define. * m32r.c (WANT_CPU,WANT_CPU_M32R): Define. (m32r_{fetch,store}_register): New functions. (model_mark_{get,set}_h_gr): Prefix with m32r_. (m32r_model_mark_{busy,unbusy}_reg): Prefix with m32r_. (h_cr_{get,set}): Prefix with m32r_. (do_trap): Fetch state from current_cpu, not current_state. Call sim_engine_halt instead of engine_halt. * sim-if.c (alloc_cpu): New function. (free_state): New function. (sim_open): Call sim_state_alloc, and malloc space for selected cpu type. Call sim_analyze_program. (sim_create_inferior): Handle selected cpu type when setting PC. start-sanitize-m32rx (sim_resume): Handle m32rx. end-sanitize-m32rx (sim_stop_reason): Deleted. (print_m32r_misc_cpu): Update. start-sanitize-m32rx (sim_{fetch,store}_register): Handle m32rx. end-sanitize-m32rx (sim_{read,write}): Deleted. (sim_engine_illegal_insn): New function. * sim-main.h: Don't include arch-defs.h,sim-core.h,sim-events.h. Include arch.h,cpuall.h. Include cpu.h,decode.h if m32r. start-sanitize-m32rx Include cpux.h,decodex.h if m32rx. end-sanitize-m32rx (_sim_cpu): Include member appropriate cpu_data member for the cpu. (M32R_MISC_PROFILE): Renamed from M32R_PROFILE. (sim_state): Delete members core,events,halt_jmp_buf. Change `cpu' member to be a pointer to the cpu's struct, rather than record inside the state struct. * tconfig.in (WITH_DEVICES): Define here. (WITH_FAST,WITH_SEM_SWITCH_{FULL,FAST}): Define for the cpu. --- sim/m32r/tconfig.in | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 sim/m32r/tconfig.in (limited to 'sim/m32r/tconfig.in') diff --git a/sim/m32r/tconfig.in b/sim/m32r/tconfig.in new file mode 100644 index 0000000..b6f03d7 --- /dev/null +++ b/sim/m32r/tconfig.in @@ -0,0 +1,35 @@ +/* M32R target configuration file. -*- C -*- */ + +/* Define this if the simulator can vary the size of memory. + See the xxx simulator for an example. + This enables the `-m size' option. + The memory size is stored in STATE_MEM_SIZE. */ +/* Not used for M32R since we use the memory module. */ +/* #define SIM_HAVE_MEM_SIZE */ + +/* For MSPR support. FIXME: revisit. */ +#define WITH_DEVICES 1 + +/* The semantic code should probably always use a switch(). + However, in case that's not possible in some circumstance, we allow + the target to choose. Perhaps this can be autoconf'd on whether the + switch is too big? I can't (yet) think of a reason for allowing the + user to choose, though the developer may certainly wish to. */ +#ifdef WANT_CPU_M32R +#define WITH_FAST 1 +#define WITH_SEM_SWITCH_FULL 0 +#define WITH_SEM_SWITCH_FAST 1 +#endif + +#ifdef WANT_CPU_M32RX +#define HAVE_PARALLEL_EXEC +#define WITH_FAST 0 +#define WITH_SEM_SWITCH_FULL 1 +#define WITH_SEM_SWITCH_FAST 0 +/* The m32rx currently never uses the scache. So hardcode this off. */ +#undef WITH_SCACHE +#define WITH_SCACHE 0 +#endif + +/* ??? Temporary hack until model support unified. */ +#define SIM_HAVE_MODEL -- cgit v1.1