From c7a48b9ac9215f67421a769c2986b6eb2a69780b Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Mon, 1 Mar 2004 09:42:33 +0000 Subject: cpu/ * frv.cpu (nsdiv, nudiv, nsdivi, nudivi): Remove fr400 profiling unit. (scutss): Change unit to I0. (calll, callil, ccalll): Add missing FR550-MAJOR and profile unit. (mqsaths): Fix FR400-MAJOR categorization. (media-quad-multiply-cross-acc, media-quad-cross-multiply-cross-acc) (media-quad-cross-multiply-acc): Change unit from MDUALACC to FMALL. * frv.opc (fr400_check_insn_major_constraints): Check for (M-2,M-1) combinations. opcodes/ * frv-desc.c, frv-opc.c: Regenerate. sim/frv/ * cache.c (frv_cache_init): Change fr400 cache statistics to match the fr405. (non_cache_access): Add missing breaks. * interrupts.c (set_exception_status_registers): Always set EAR15 for data_access_errors. * memory.c (fr400_check_write_address): Remove redundant alignment check. * model.c: Regenerate. --- sim/frv/ChangeLog | 11 +++++++ sim/frv/cache.c | 5 ++- sim/frv/interrupts.c | 3 +- sim/frv/memory.c | 12 ------- sim/frv/model.c | 89 +++++++++++++++++++++++----------------------------- 5 files changed, 55 insertions(+), 65 deletions(-) (limited to 'sim/frv') diff --git a/sim/frv/ChangeLog b/sim/frv/ChangeLog index 652c956..73a6a84 100644 --- a/sim/frv/ChangeLog +++ b/sim/frv/ChangeLog @@ -1,5 +1,16 @@ 2004-03-01 Richard Sandiford + * cache.c (frv_cache_init): Change fr400 cache statistics to match + the fr405. + (non_cache_access): Add missing breaks. + * interrupts.c (set_exception_status_registers): Always set EAR15 + for data_access_errors. + * memory.c (fr400_check_write_address): Remove redundant alignment + check. + * model.c: Regenerate. + +2004-03-01 Richard Sandiford + * frv.c (frvbf_iacc_cut): Rework, taking rounding into account. 2004-03-01 Richard Sandiford diff --git a/sim/frv/cache.c b/sim/frv/cache.c index 7b2635b..578a011 100644 --- a/sim/frv/cache.c +++ b/sim/frv/cache.c @@ -39,7 +39,7 @@ frv_cache_init (SIM_CPU *cpu, FRV_CACHE *cache) { case bfd_mach_fr400: if (cache->configured_sets == 0) - cache->configured_sets = 128; + cache->configured_sets = 512; if (cache->configured_ways == 0) cache->configured_ways = 2; if (cache->line_size == 0) @@ -208,6 +208,7 @@ non_cache_access (FRV_CACHE *cache, USI address) if (address >= 0xff000000 || address >= 0xfe000000 && address <= 0xfeffffff) return 1; /* non-cache access */ + break; case bfd_mach_fr550: if (address >= 0xff000000 || address >= 0xfeff0000 && address <= 0xfeffffff) @@ -219,6 +220,7 @@ non_cache_access (FRV_CACHE *cache, USI address) } else if (address >= 0xfe400000 && address <= 0xfe407fff) return 1; /* non-cache access */ + break; default: if (address >= 0xff000000 || address >= 0xfeff0000 && address <= 0xfeffffff) @@ -230,6 +232,7 @@ non_cache_access (FRV_CACHE *cache, USI address) } else if (address >= 0xfe400000 && address <= 0xfe403fff) return 1; /* non-cache access */ + break; } hsr0 = GET_HSR0 (); diff --git a/sim/frv/interrupts.c b/sim/frv/interrupts.c index 540ee06..1496fc5 100644 --- a/sim/frv/interrupts.c +++ b/sim/frv/interrupts.c @@ -845,8 +845,7 @@ set_exception_status_registers ( break; case FRV_DATA_ACCESS_ERROR: reg_index = 15; /* Use ESR15, EPCR15. */ - if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr400) - set_ear = 1; + set_ear = 1; break; case FRV_DATA_ACCESS_EXCEPTION: set_daec = 1; diff --git a/sim/frv/memory.c b/sim/frv/memory.c index 4dbc652..adee4c1 100644 --- a/sim/frv/memory.c +++ b/sim/frv/memory.c @@ -679,18 +679,6 @@ frvbf_read_imem_USI (SIM_CPU *current_cpu, PCADDR vpc) static SI fr400_check_write_address (SIM_CPU *current_cpu, SI address, int align_mask) { - if (address & align_mask) - { - /* On the fr400, this causes a data_access_error. */ - /* Make sure that this exception is not masked. */ - USI isr = GET_ISR (); - if (! GET_ISR_EMAM (isr)) - { - /* Bad alignment causes a data_access_error on fr400. */ - frv_queue_data_access_error_interrupt (current_cpu, address); - } - address &= ~align_mask; - } if (align_mask == 7 && address >= 0xfe800000 && address <= 0xfeffffff) frv_queue_program_interrupt (current_cpu, FRV_DATA_STORE_ERROR); diff --git a/sim/frv/model.c b/sim/frv/model.c index 14c268b..0fa5d4b 100644 --- a/sim/frv/model.c +++ b/sim/frv/model.c @@ -20263,7 +20263,16 @@ model_fr550_calll (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); } return cycles; #undef FLD @@ -20302,7 +20311,14 @@ model_fr550_callil (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + referenced |= 1 << 0; + referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); } return cycles; #undef FLD @@ -23424,7 +23440,16 @@ model_fr550_ccalll (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); } return cycles; #undef FLD @@ -57775,17 +57800,7 @@ model_fr400_nsdiv (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT in_GRi = -1; - INT in_GRj = -1; - INT out_GRk = -1; - INT out_ICCi_1 = -1; - in_GRi = FLD (in_GRi); - in_GRj = FLD (in_GRj); - out_GRk = FLD (out_GRk); - referenced |= 1 << 0; - referenced |= 1 << 1; - referenced |= 1 << 2; - cycles += frvbf_model_fr400_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); } return cycles; #undef FLD @@ -57827,17 +57842,7 @@ model_fr400_nudiv (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT in_GRi = -1; - INT in_GRj = -1; - INT out_GRk = -1; - INT out_ICCi_1 = -1; - in_GRi = FLD (in_GRi); - in_GRj = FLD (in_GRj); - out_GRk = FLD (out_GRk); - referenced |= 1 << 0; - referenced |= 1 << 1; - referenced |= 1 << 2; - cycles += frvbf_model_fr400_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); } return cycles; #undef FLD @@ -59267,15 +59272,7 @@ model_fr400_nsdivi (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT in_GRi = -1; - INT in_GRj = -1; - INT out_GRk = -1; - INT out_ICCi_1 = -1; - in_GRi = FLD (in_GRi); - out_GRk = FLD (out_GRk); - referenced |= 1 << 0; - referenced |= 1 << 2; - cycles += frvbf_model_fr400_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); } return cycles; #undef FLD @@ -59315,15 +59312,7 @@ model_fr400_nudivi (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT in_GRi = -1; - INT in_GRj = -1; - INT out_GRk = -1; - INT out_ICCi_1 = -1; - in_GRi = FLD (in_GRi); - out_GRk = FLD (out_GRk); - referenced |= 1 << 0; - referenced |= 1 << 2; - cycles += frvbf_model_fr400_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); } return cycles; #undef FLD @@ -86433,9 +86422,9 @@ static const INSN_TIMING fr550_timing[] = { { FRVBF_INSN_FCBULR, model_fr550_fcbulr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, { FRVBF_INSN_FCBOLR, model_fr550_fcbolr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, { FRVBF_INSN_JMPL, model_fr550_jmpl, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, - { FRVBF_INSN_CALLL, model_fr550_calll, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CALLL, model_fr550_calll, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, { FRVBF_INSN_JMPIL, model_fr550_jmpil, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, - { FRVBF_INSN_CALLIL, model_fr550_callil, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CALLIL, model_fr550_callil, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, { FRVBF_INSN_CALL, model_fr550_call, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, { FRVBF_INSN_RETT, model_fr550_rett, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, { FRVBF_INSN_REI, model_fr550_rei, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, @@ -86580,7 +86569,7 @@ static const INSN_TIMING fr550_timing[] = { { FRVBF_INSN_CFCKU, model_fr550_cfcku, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, { FRVBF_INSN_CFCKO, model_fr550_cfcko, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, { FRVBF_INSN_CJMPL, model_fr550_cjmpl, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, - { FRVBF_INSN_CCALLL, model_fr550_ccalll, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCALLL, model_fr550_ccalll, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, { FRVBF_INSN_ICI, model_fr550_ici, { { (int) UNIT_FR550_U_ICI, 1, 1 } } }, { FRVBF_INSN_DCI, model_fr550_dci, { { (int) UNIT_FR550_U_DCI, 1, 1 } } }, { FRVBF_INSN_ICEI, model_fr550_icei, { { (int) UNIT_FR550_U_ICI, 1, 1 } } }, @@ -88323,9 +88312,9 @@ static const INSN_TIMING fr400_timing[] = { { FRVBF_INSN_XOR, model_fr400_xor, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, { FRVBF_INSN_NOT, model_fr400_not, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, { FRVBF_INSN_SDIV, model_fr400_sdiv, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } }, - { FRVBF_INSN_NSDIV, model_fr400_nsdiv, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_NSDIV, model_fr400_nsdiv, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, { FRVBF_INSN_UDIV, model_fr400_udiv, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } }, - { FRVBF_INSN_NUDIV, model_fr400_nudiv, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_NUDIV, model_fr400_nudiv, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, { FRVBF_INSN_SMUL, model_fr400_smul, { { (int) UNIT_FR400_U_IMUL, 1, 1 } } }, { FRVBF_INSN_UMUL, model_fr400_umul, { { (int) UNIT_FR400_U_IMUL, 1, 1 } } }, { FRVBF_INSN_SMU, model_fr400_smu, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, @@ -88381,9 +88370,9 @@ static const INSN_TIMING fr400_timing[] = { { FRVBF_INSN_ORI, model_fr400_ori, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, { FRVBF_INSN_XORI, model_fr400_xori, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, { FRVBF_INSN_SDIVI, model_fr400_sdivi, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } }, - { FRVBF_INSN_NSDIVI, model_fr400_nsdivi, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_NSDIVI, model_fr400_nsdivi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, { FRVBF_INSN_UDIVI, model_fr400_udivi, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } }, - { FRVBF_INSN_NUDIVI, model_fr400_nudivi, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_NUDIVI, model_fr400_nudivi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, { FRVBF_INSN_SMULI, model_fr400_smuli, { { (int) UNIT_FR400_U_IMUL, 1, 1 } } }, { FRVBF_INSN_UMULI, model_fr400_umuli, { { (int) UNIT_FR400_U_IMUL, 1, 1 } } }, { FRVBF_INSN_SLLI, model_fr400_slli, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, -- cgit v1.1