From 9420287ed25a0cc7ef77fcc95ccab3f13d4614e3 Mon Sep 17 00:00:00 2001 From: Andrew Cagney Date: Tue, 2 Dec 1997 06:37:09 +0000 Subject: For "mulxu", store unsigned product in ACC. Test. --- sim/d10v/ChangeLog | 1 + sim/d10v/simops.c | 9 ++++++--- 2 files changed, 7 insertions(+), 3 deletions(-) (limited to 'sim/d10v') diff --git a/sim/d10v/ChangeLog b/sim/d10v/ChangeLog index d801cb2..b1a9568 100644 --- a/sim/d10v/ChangeLog +++ b/sim/d10v/ChangeLog @@ -2,6 +2,7 @@ Tue Dec 2 15:01:08 1997 Andrew Cagney * simops.c (OP_3A00): For "macu", perform multiply stage using 32 bit rather than 16 bit precision. + (OP_3C00): For "mulxu", store unsigned product in ACC. Tue Dec 2 11:04:37 1997 Andrew Cagney diff --git a/sim/d10v/simops.c b/sim/d10v/simops.c index 6f12e5a..e5a0825 100644 --- a/sim/d10v/simops.c +++ b/sim/d10v/simops.c @@ -1577,11 +1577,14 @@ OP_1C00 () void OP_3C00 () { - int64 tmp; + uint64 tmp; + uint32 src1; + uint32 src2; trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG); - tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]); - + src1 = (uint16) State.regs[OP[1]]; + src2 = (uint16) State.regs[OP[2]]; + tmp = src1 * src2; if (State.FX) tmp <<= 1; -- cgit v1.1