From e514a9d64262fcceccd85180b20b7adc3c4a5eed Mon Sep 17 00:00:00 2001 From: Jason Molenda Date: Tue, 26 Oct 1999 03:43:48 +0000 Subject: import gdb-1999-10-25 snapshot --- sim/common/ChangeLog | 15 +++++++++++++++ sim/common/cgen-par.c | 41 ++++++++++++++++++++++++++++++++++++----- sim/common/cgen-par.h | 8 ++++++++ 3 files changed, 59 insertions(+), 5 deletions(-) (limited to 'sim/common') diff --git a/sim/common/ChangeLog b/sim/common/ChangeLog index a1df5fe..1d8bfea 100644 --- a/sim/common/ChangeLog +++ b/sim/common/ChangeLog @@ -1,3 +1,18 @@ +1999-10-22 Dave Brolley + + * cgen-par.h (insn_address): New field in CGEN_WRITE_QUEUE_ELEMENT. + (CGEN_WRITE_QUEUE_ELEMENT_IADDR): New macro. + * cgen-par.c: Set insn_address for each queued write. Get pc from + cpu when executing queued writes. + +1999-10-19 Dave Brolley + + * cgen-par.h (sim_queue_fn_pc_write): New function. + (CGEN_FN_PC_WRITE): New enumerator. + (fn_pc_write): New union member. + * cgen-par.c (sim_queue_fn_pc_write): New function. + (cgen_write_queue_element_execute): Handle CGEN_FN_PC_WRITE. + 1999-10-18 Dave Brolley * cgen-par.h (CGEN_MEM_DI_WRITE): New enumerator. diff --git a/sim/common/cgen-par.c b/sim/common/cgen-par.c index d6450db..e2af54e 100644 --- a/sim/common/cgen-par.c +++ b/sim/common/cgen-par.c @@ -29,6 +29,7 @@ void sim_queue_bi_write (SIM_CPU *cpu, BI *target, BI value) CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu); CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q); element->kind = CGEN_BI_WRITE; + element->insn_address = CPU_PC_GET (cpu); element->kinds.bi_write.target = target; element->kinds.bi_write.value = value; } @@ -38,6 +39,7 @@ void sim_queue_qi_write (SIM_CPU *cpu, UQI *target, UQI value) CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu); CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q); element->kind = CGEN_QI_WRITE; + element->insn_address = CPU_PC_GET (cpu); element->kinds.qi_write.target = target; element->kinds.qi_write.value = value; } @@ -47,6 +49,7 @@ void sim_queue_si_write (SIM_CPU *cpu, SI *target, SI value) CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu); CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q); element->kind = CGEN_SI_WRITE; + element->insn_address = CPU_PC_GET (cpu); element->kinds.si_write.target = target; element->kinds.si_write.value = value; } @@ -56,6 +59,7 @@ void sim_queue_sf_write (SIM_CPU *cpu, SI *target, SF value) CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu); CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q); element->kind = CGEN_SF_WRITE; + element->insn_address = CPU_PC_GET (cpu); element->kinds.sf_write.target = target; element->kinds.sf_write.value = value; } @@ -65,6 +69,7 @@ void sim_queue_pc_write (SIM_CPU *cpu, USI value) CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu); CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q); element->kind = CGEN_PC_WRITE; + element->insn_address = CPU_PC_GET (cpu); element->kinds.pc_write.value = value; } @@ -78,6 +83,7 @@ void sim_queue_fn_hi_write ( CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu); CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q); element->kind = CGEN_FN_HI_WRITE; + element->insn_address = CPU_PC_GET (cpu); element->kinds.fn_hi_write.function = write_function; element->kinds.fn_hi_write.regno = regno; element->kinds.fn_hi_write.value = value; @@ -93,6 +99,7 @@ void sim_queue_fn_si_write ( CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu); CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q); element->kind = CGEN_FN_SI_WRITE; + element->insn_address = CPU_PC_GET (cpu); element->kinds.fn_si_write.function = write_function; element->kinds.fn_si_write.regno = regno; element->kinds.fn_si_write.value = value; @@ -108,6 +115,7 @@ void sim_queue_fn_di_write ( CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu); CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q); element->kind = CGEN_FN_DI_WRITE; + element->insn_address = CPU_PC_GET (cpu); element->kinds.fn_di_write.function = write_function; element->kinds.fn_di_write.regno = regno; element->kinds.fn_di_write.value = value; @@ -123,16 +131,32 @@ void sim_queue_fn_df_write ( CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu); CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q); element->kind = CGEN_FN_DF_WRITE; + element->insn_address = CPU_PC_GET (cpu); element->kinds.fn_df_write.function = write_function; element->kinds.fn_df_write.regno = regno; element->kinds.fn_df_write.value = value; } +void sim_queue_fn_pc_write ( + SIM_CPU *cpu, + void (*write_function)(SIM_CPU *cpu, USI), + USI value +) +{ + CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu); + CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q); + element->kind = CGEN_FN_PC_WRITE; + element->insn_address = CPU_PC_GET (cpu); + element->kinds.fn_pc_write.function = write_function; + element->kinds.fn_pc_write.value = value; +} + void sim_queue_mem_qi_write (SIM_CPU *cpu, SI address, QI value) { CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu); CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q); element->kind = CGEN_MEM_QI_WRITE; + element->insn_address = CPU_PC_GET (cpu); element->kinds.mem_qi_write.address = address; element->kinds.mem_qi_write.value = value; } @@ -142,6 +166,7 @@ void sim_queue_mem_hi_write (SIM_CPU *cpu, SI address, HI value) CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu); CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q); element->kind = CGEN_MEM_HI_WRITE; + element->insn_address = CPU_PC_GET (cpu); element->kinds.mem_hi_write.address = address; element->kinds.mem_hi_write.value = value; } @@ -151,6 +176,7 @@ void sim_queue_mem_si_write (SIM_CPU *cpu, SI address, SI value) CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu); CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q); element->kind = CGEN_MEM_SI_WRITE; + element->insn_address = CPU_PC_GET (cpu); element->kinds.mem_si_write.address = address; element->kinds.mem_si_write.value = value; } @@ -160,6 +186,7 @@ void sim_queue_mem_di_write (SIM_CPU *cpu, SI address, DI value) CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu); CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q); element->kind = CGEN_MEM_DI_WRITE; + element->insn_address = CPU_PC_GET (cpu); element->kinds.mem_di_write.address = address; element->kinds.mem_di_write.value = value; } @@ -169,6 +196,7 @@ void sim_queue_mem_df_write (SIM_CPU *cpu, SI address, DF value) CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu); CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q); element->kind = CGEN_MEM_DF_WRITE; + element->insn_address = CPU_PC_GET (cpu); element->kinds.mem_df_write.address = address; element->kinds.mem_df_write.value = value; } @@ -215,28 +243,31 @@ cgen_write_queue_element_execute (SIM_CPU *cpu, CGEN_WRITE_QUEUE_ELEMENT *item) item->kinds.fn_df_write.regno, item->kinds.fn_df_write.value); break; + case CGEN_FN_PC_WRITE: + item->kinds.fn_pc_write.function (cpu, item->kinds.fn_pc_write.value); + break; case CGEN_MEM_QI_WRITE: - pc = CPU_PC_GET (cpu); + pc = item->insn_address; SETMEMQI (cpu, pc, item->kinds.mem_qi_write.address, item->kinds.mem_qi_write.value); break; case CGEN_MEM_HI_WRITE: - pc = CPU_PC_GET (cpu); + pc = item->insn_address; SETMEMHI (cpu, pc, item->kinds.mem_hi_write.address, item->kinds.mem_hi_write.value); break; case CGEN_MEM_SI_WRITE: - pc = CPU_PC_GET (cpu); + pc = item->insn_address; SETMEMSI (cpu, pc, item->kinds.mem_si_write.address, item->kinds.mem_si_write.value); break; case CGEN_MEM_DI_WRITE: - pc = CPU_PC_GET (cpu); + pc = item->insn_address; SETMEMDI (cpu, pc, item->kinds.mem_di_write.address, item->kinds.mem_di_write.value); break; case CGEN_MEM_DF_WRITE: - pc = CPU_PC_GET (cpu); + pc = item->insn_address; SETMEMDF (cpu, pc, item->kinds.mem_df_write.address, item->kinds.mem_df_write.value); break; diff --git a/sim/common/cgen-par.h b/sim/common/cgen-par.h index c786d1c..9cf5e8c 100644 --- a/sim/common/cgen-par.h +++ b/sim/common/cgen-par.h @@ -26,6 +26,7 @@ enum cgen_write_queue_kind { CGEN_BI_WRITE, CGEN_QI_WRITE, CGEN_SI_WRITE, CGEN_SF_WRITE, CGEN_PC_WRITE, CGEN_FN_HI_WRITE, CGEN_FN_SI_WRITE, CGEN_FN_DI_WRITE, CGEN_FN_DF_WRITE, + CGEN_FN_PC_WRITE, CGEN_MEM_QI_WRITE, CGEN_MEM_HI_WRITE, CGEN_MEM_SI_WRITE, CGEN_MEM_DI_WRITE, CGEN_MEM_DF_WRITE, CGEN_NUM_WRITE_KINDS @@ -34,6 +35,7 @@ enum cgen_write_queue_kind { /* Element of the write queue. */ typedef struct { enum cgen_write_queue_kind kind; /* Used to select union member below. */ + IADDR insn_address; /* Address of the insn performing the write. */ union { struct { BI *target; @@ -75,6 +77,10 @@ typedef struct { void (*function)(SIM_CPU *, UINT, DI); } fn_df_write; struct { + USI value; + void (*function)(SIM_CPU *, USI); + } fn_pc_write; + struct { SI address; QI value; } mem_qi_write; @@ -98,6 +104,7 @@ typedef struct { } CGEN_WRITE_QUEUE_ELEMENT; #define CGEN_WRITE_QUEUE_ELEMENT_KIND(element) ((element)->kind) +#define CGEN_WRITE_QUEUE_ELEMENT_IADDR(element) ((element)->insn_address) extern void cgen_write_queue_element_execute ( SIM_CPU *, CGEN_WRITE_QUEUE_ELEMENT * @@ -136,6 +143,7 @@ extern void sim_queue_fn_hi_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, UHI), UI extern void sim_queue_fn_si_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, USI), UINT, SI); extern void sim_queue_fn_di_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, DI), UINT, DI); extern void sim_queue_fn_df_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, DI), UINT, DF); +extern void sim_queue_fn_pc_write (SIM_CPU *, void (*)(SIM_CPU *, USI), USI); extern void sim_queue_mem_qi_write (SIM_CPU *, SI, QI); extern void sim_queue_mem_hi_write (SIM_CPU *, SI, HI); -- cgit v1.1