From e8f42b5e36b2083e36855007442aff110291b6aa Mon Sep 17 00:00:00 2001 From: Jim Wilson Date: Tue, 14 Feb 2017 14:31:03 -0800 Subject: Add ldn/stn single support, fix ldnr support. sim/aarch64/ * simulator.c: (LDn_STn_SINGLE_LANE_AND_SIZE): New. (do_vec_LDn_single, do_vec_STn_single): New. (do_vec_LDnR): Add and set new nregs var. Replace switch on nregs with loop over nregs using new var n. Add n times size to address in loop. Add n to vd in loop. (do_vec_load_store): Add comment for instruction bit 24. New var single to hold instruction bit 24. Add new code to use single. Move ldnr support inside single if statements. Fix ldnr register counts inside post if statement. Change HALT_NYI calls to HALT_UNALLOC. sim/testsuite/sim/aarch64/ * ldn_single.s: New. * ldnr.s: New. * stn_single.s: New. --- sim/aarch64/ChangeLog | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'sim/aarch64/ChangeLog') diff --git a/sim/aarch64/ChangeLog b/sim/aarch64/ChangeLog index f9a62e7..2a21fc3 100644 --- a/sim/aarch64/ChangeLog +++ b/sim/aarch64/ChangeLog @@ -1,3 +1,15 @@ +2017-02-14 Jim Wilson + + * simulator.c: (LDn_STn_SINGLE_LANE_AND_SIZE): New. + (do_vec_LDn_single, do_vec_STn_single): New. + (do_vec_LDnR): Add and set new nregs var. Replace switch on nregs with + loop over nregs using new var n. Add n times size to address in loop. + Add n to vd in loop. + (do_vec_load_store): Add comment for instruction bit 24. New var + single to hold instruction bit 24. Add new code to use single. Move + ldnr support inside single if statements. Fix ldnr register counts + inside post if statement. Change HALT_NYI calls to HALT_UNALLOC. + 2017-01-23 Jim Wilson * simulator.c (do_vec_compare): Add case 0x23 for CMTST. -- cgit v1.1