From bf1554384b186b448904dbc13ee5374239c88520 Mon Sep 17 00:00:00 2001 From: Jim Wilson Date: Sat, 22 Apr 2017 16:36:01 -0700 Subject: Fix ldn/stn multiple instructions. Fix testcases with unaligned data. sim/aarch64/ * simulator.c (vec_load): Add M argument. Rewrite to iterate over registers based on structure size. (LD4, LD3, LD2, LD1_2, LD1_3, LD1_4): Pass new arg to vec_load. (LD1_1): Replace with call to vec_load. (vec_store): Add new M argument. Rewrite to iterate over registers based on structure size. (ST4, ST3, ST2, ST1_2, ST1_3, ST1_4): Pass new arg to vec_store. (ST1_1): Replace with call to vec_store. sim/testsuite/sim/aarch64/ * fcvtz.s, fstur.s, ldn_single.s, ldnr.s, mla.s, mls.s, uzp.s: Align data. * sumulh.s: Delete unnecessary data alignment. * stn_single.s: Align data. Fix unaligned ldr insns. Adjust cmp arguments to match change. * ldn_multiple.s, stn_multiple.s: New. --- sim/aarch64/ChangeLog | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'sim/aarch64/ChangeLog') diff --git a/sim/aarch64/ChangeLog b/sim/aarch64/ChangeLog index 42379df..f1574a5 100644 --- a/sim/aarch64/ChangeLog +++ b/sim/aarch64/ChangeLog @@ -1,3 +1,14 @@ +2017-04-22 Jim Wilson + + * simulator.c (vec_load): Add M argument. Rewrite to iterate over + registers based on structure size. + (LD4, LD3, LD2, LD1_2, LD1_3, LD1_4): Pass new arg to vec_load. + (LD1_1): Replace with call to vec_load. + (vec_store): Add new M argument. Rewrite to iterate over registers + based on structure size. + (ST4, ST3, ST2, ST1_2, ST1_3, ST1_4): Pass new arg to vec_store. + (ST1_1): Replace with call to vec_store. + 2017-04-08 Jim Wilson * simulator.c (do_vec_FCVTL): New. -- cgit v1.1