From f4791f1afad449b81804cb6b62ed238603592d1b Mon Sep 17 00:00:00 2001 From: Alan Modra Date: Mon, 11 May 2020 09:32:56 +0930 Subject: Power10 vector integer multiply, divide, modulo insns opcodes/ * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld, vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw, vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd. gas/ * testsuite/gas/ppc/vec_mul.s, * testsuite/gas/ppc/vec_mul.d: New test. * testsuite/gas/ppc/ppc.exp: Run it. --- opcodes/ChangeLog | 6 ++++++ opcodes/ppc-opc.c | 17 +++++++++++++++++ 2 files changed, 23 insertions(+) (limited to 'opcodes') diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index f3ad3a1..0958a3b 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,9 @@ +2020-05-11 Alan Modra + + * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld, + vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw, + vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd. + 2020-05-11 Peter Bergner * ppc-opc.c (powerpc_opcodes) : New mnemonics. diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index 927a892..5cd5cd9 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -3983,6 +3983,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"vcmpnew", VXR(4, 135,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, {"vmulouw", VX (4, 136), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, {"vmuluwm", VX (4, 137), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, +{"vdivuw", VX (4, 139), VX_MASK, POWER10, 0, {VD, VA, VB}}, {"vmrghw", VX (4, 140), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"vpkuhus", VX (4, 142), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, 0, {FRT, FRB}}, @@ -3996,6 +3997,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"vrldmi", VX (4, 197), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, {"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, {"vcmpequd", VXR(4, 199,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, +{"vdivud", VX (4, 203), VX_MASK, POWER10, 0, {VD, VA, VB}}, {"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"machhws", XO (4, 108,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, {"machhws.", XO (4, 108,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, @@ -4036,6 +4038,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"vcmpnezw", VXR(4, 391,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, {"vmulosw", VX (4, 392), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, {"vexptefp", VX (4, 394), VXVA_MASK, PPCVEC, 0, {VD, VB}}, +{"vdivsw", VX (4, 395), VX_MASK, POWER10, 0, {VD, VA, VB}}, {"vmrglw", VX (4, 396), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"vpkshss", VX (4, 398), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"macchwsu", XO (4, 204,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, @@ -4044,7 +4047,9 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"vsl", VX (4, 452), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"vrldnm", VX (4, 453), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, {"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, +{"vmulld", VX (4, 457), VX_MASK, POWER10, 0, {VD, VA, VB}}, {"vlogefp", VX (4, 458), VXVA_MASK, PPCVEC, 0, {VD, VB}}, +{"vdivsd", VX (4, 459), VX_MASK, POWER10, 0, {VD, VA, VB}}, {"vpkswss", VX (4, 462), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"macchws", XO (4, 236,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, {"macchws.", XO (4, 236,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, @@ -4134,9 +4139,11 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"evfssqrt", VX_RB_CONST(4, 647, 0), VX_RB_CONST_MASK, PPCEFS2, 0, {RD, RA}}, {"vmuleuw", VX (4, 648), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, {"evfsmul", VX (4, 648), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, +{"vmulhuw", VX (4, 649), VX_MASK, POWER10, 0, {VD, VA, VB}}, {"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"evfsnmadd", VX (4, 650), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"vrfip", VX (4, 650), VXVA_MASK, PPCVEC, 0, {VD, VB}}, +{"vdiveuw", VX (4, 651), VX_MASK, POWER10, 0, {VD, VA, VB}}, {"evfsnmsub", VX (4, 651), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, {"vspltw", VX (4, 652), VXUIMM2_MASK, PPCVEC, 0, {VD, VB, UIMM2}}, @@ -4193,9 +4200,11 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"efssqrt", VX_RB_CONST(4, 711, 0), VX_RB_CONST_MASK,PPCEFS2, 0, {RD, RA}}, {"vcmpgtud", VXR(4, 711,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, {"efsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, +{"vmulhud", VX (4, 713), VX_MASK, POWER10, 0, {VD, VA, VB}}, {"efsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, {"efsnmadd", VX (4, 714), VX_MASK, PPCEFS2, 0, {RS, RA, RB}}, {"vrfim", VX (4, 714), VXVA_MASK, PPCVEC, 0, {VD, VB}}, +{"vdiveud", VX (4, 715), VX_MASK, POWER10, 0, {VD, VA, VB}}, {"efsnmsub", VX (4, 715), VX_MASK, PPCEFS2, 0, {RS, RA, RB}}, {"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, {"vextractd", VX (4, 717), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, @@ -4331,8 +4340,10 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"vsraw", VX (4, 900), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, {"vmulesw", VX (4, 904), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, +{"vmulhsw", VX (4, 905), VX_MASK, POWER10, 0, {VD, VA, VB}}, {"vctuxs", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, {"vcfpuxws", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, +{"vdivesw", VX (4, 907), VX_MASK, POWER10, 0, {VD, VA, VB}}, {"vspltisw", VX (4, 908), VXVB_MASK, PPCVEC, 0, {VD, SIMM}}, {"vinsertw", VX (4, 909), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, {"maclhwsu", XO (4, 460,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, @@ -4341,8 +4352,10 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"vsrad", VX (4, 964), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, {"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, {"vcmpgtsd", VXR(4, 967,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, +{"vmulhsd", VX (4, 969), VX_MASK, POWER10, 0, {VD, VA, VB}}, {"vctsxs", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, {"vcfpsxws", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, +{"vdivesd", VX (4, 971), VX_MASK, POWER10, 0, {VD, VA, VB}}, {"vinsertd", VX (4, 973), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, {"vupklpx", VX (4, 974), VXVA_MASK, PPCVEC, 0, {VD, VB}}, {"maclhws", XO (4, 492,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, @@ -4632,6 +4645,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"udi10fcm.", APU(4, 835,0), APU_MASK, PPC440, 0, {URT, URA, URB}}, {"udi10fcm", APU(4, 835,1), APU_MASK, PPC440, 0, {URT, URA, URB}}, {"vsum2sws", VX (4,1672), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, +{"vmoduw", VX (4,1675), VX_MASK, POWER10, 0, {VD, VA, VB}}, {"vmrgow", VX (4,1676), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, {"vextuwlx", VX (4,1677), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, {"vshasigmad", VX (4,1730), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}}, @@ -4640,6 +4654,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"udi11fcm.", APU(4, 867,0), APU_MASK, PPC440, 0, {URT, URA, URB}}, {"vcmpgtud.", VXR(4, 711,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, {"udi11fcm", APU(4, 867,1), APU_MASK, PPC440, 0, {URT, URA, URB}}, +{"vmodud", VX (4,1739), VX_MASK, POWER10, 0, {VD, VA, VB}}, {"vupklsw", VX (4,1742), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, {"vsubsbs", VX (4,1792), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"vclzb", VX (4,1794), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, @@ -4671,6 +4686,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"udi14fcm.", APU(4, 963,0), APU_MASK, PPC440, 0, {URT, URA, URB}}, {"udi14fcm", APU(4, 963,1), APU_MASK, PPC440, 0, {URT, URA, URB}}, {"vsumsws", VX (4,1928), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, +{"vmodsw", VX (4,1931), VX_MASK, POWER10, 0, {VD, VA, VB}}, {"vmrgew", VX (4,1932), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, {"vextuwrx", VX (4,1933), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, {"maclhwsuo", XO (4, 460,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, @@ -4681,6 +4697,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"udi15fcm.", APU(4, 995,0), APU_MASK, PPC440, 0, {URT, URA, URB}}, {"vcmpgtsd.", VXR(4, 967,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, {"udi15fcm", APU(4, 995,1), APU_MASK, PPC440, 0, {URT, URA, URB}}, +{"vmodsd", VX (4,1995), VX_MASK, POWER10, 0, {VD, VA, VB}}, {"maclhwso", XO (4, 492,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, {"maclhwso.", XO (4, 492,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, {"nmaclhwso", XO (4, 494,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, -- cgit v1.1