From c7a5aa9c64fc5b4fd7de8119dd6597127060e884 Mon Sep 17 00:00:00 2001 From: Peter Bergner Date: Fri, 5 Oct 2012 14:06:20 +0000 Subject: opcodes/ * ppc-dis.c (ppc_opts) : Use PPC_OPCODE_ALTIVEC2; * ppc-opc.c (VBA): New define. (powerpc_opcodes) : New extended mnemonics. gas/testsuite/ * gas/ppc/power7.d: Add tests for mfppr, mfppr32, mtppr and mtppr32. * gas/ppc/power7.s: Likewise. * gas/ppc/altivec.d: Add tests for all legacy Altivec instructions. * gas/ppc/altivec.s: Likewise. * gas/ppc/altivec2.d: New test file. * gas/ppc/altivec2.s: Likewise. * gas/ppc/ppc.exp: Run it. --- opcodes/ChangeLog | 7 +++++++ opcodes/ppc-dis.c | 2 +- opcodes/ppc-opc.c | 13 +++++++++++++ 3 files changed, 21 insertions(+), 1 deletion(-) (limited to 'opcodes') diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 214ea81..ea9d742 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,10 @@ +2012-10-05 Peter Bergner + + * ppc-dis.c (ppc_opts) : Use PPC_OPCODE_ALTIVEC2; + * ppc-opc.c (VBA): New define. + (powerpc_opcodes) : New extended mnemonics. + 2012-10-04 Nick Clifton * v850-dis.c (disassemble): Place square parentheses around second diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c index 44310e8..03b3160 100644 --- a/opcodes/ppc-dis.c +++ b/opcodes/ppc-dis.c @@ -88,7 +88,7 @@ struct ppc_mopt ppc_opts[] = { | PPC_OPCODE_A2), 0 }, { "altivec", (PPC_OPCODE_PPC), - PPC_OPCODE_ALTIVEC }, + PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 }, { "any", 0, PPC_OPCODE_ANY }, { "booke", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE), diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index 6ebcc90..cbf264b 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -156,6 +156,9 @@ const struct powerpc_operand powerpc_operands[] = /* The BB field in an XL form instruction when it must be the same as the BA field in the same instruction. */ #define BBA BB + 1 + /* The VB field in a VX form instruction when it must be the same + as the VA field in the same instruction. */ +#define VBA BBA { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE }, /* The BD field in a B form instruction. The lower two bits are @@ -3106,6 +3109,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"vmulesb", VX (4, 776), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_2, RA}}, {"vcfux", VX (4, 778), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}}, +{"vcuxwfp", VX (4, 778), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}}, {"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, {"vspltisb", VX (4, 780), VXVB_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, SIMM}}, {"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_2, RA}}, @@ -3146,6 +3150,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"vcmpgtsh", VXR(4, 838,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"vmulesh", VX (4, 840), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"vcfsx", VX (4, 842), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}}, +{"vcsxwfp", VX (4, 842), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}}, {"vspltish", VX (4, 844), VXVB_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, SIMM}}, {"vupkhpx", VX (4, 846), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}}, {"mullhw", XRC(4, 424,0), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, @@ -3159,11 +3164,13 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"vsraw", VX (4, 900), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"vctuxs", VX (4, 906), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}}, +{"vcfpuxws", VX (4, 906), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}}, {"vspltisw", VX (4, 908), VXVB_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, SIMM}}, {"maclhwsu", XO (4, 460,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, {"maclhwsu.", XO (4, 460,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, {"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"vctsxs", VX (4, 970), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}}, +{"vcfpsxsw", VX (4, 970), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}}, {"vupklpx", VX (4, 974), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}}, {"maclhws", XO (4, 492,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, {"maclhws.", XO (4, 492,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, @@ -3234,6 +3241,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"vsubuwm", VX (4,1152), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"vavguw", VX (4,1154), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"vabsduw", VX (4,1155), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}}, +{"vmr", VX (4,1156), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VBA}}, {"vor", VX (4,1156), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, @@ -3268,6 +3276,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"vavgsb", VX (4,1282), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, {"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"vnot", VX (4,1284), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VBA}}, {"vnor", VX (4,1284), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, {"udi4fcm.", APU(4, 643,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, @@ -4818,6 +4827,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mfdvlim", XSPR(31,339,883), XSPR_MASK, TITAN, PPCNONE, {RT}}, {"mfclcsr", XSPR(31,339,884), XSPR_MASK, TITAN, PPCNONE, {RT}}, {"mfccr1", XSPR(31,339,888), XSPR_MASK, TITAN, PPCNONE, {RT}}, +{"mfppr", XSPR(31,339,896), XSPR_MASK, POWER7, PPCNONE, {RT}}, +{"mfppr32", XSPR(31,339,898), XSPR_MASK, POWER7, PPCNONE, {RT}}, {"mfrstcfg", XSPR(31,339,923), XSPR_MASK, TITAN, PPCNONE, {RT}}, {"mfdcdbtrl", XSPR(31,339,924), XSPR_MASK, TITAN, PPCNONE, {RT}}, {"mfdcdbtrh", XSPR(31,339,925), XSPR_MASK, TITAN, PPCNONE, {RT}}, @@ -5121,6 +5132,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mtdvlim", XSPR(31,467,883), XSPR_MASK, TITAN, PPCNONE, {RS}}, {"mtclcsr", XSPR(31,467,884), XSPR_MASK, TITAN, PPCNONE, {RS}}, {"mtccr1", XSPR(31,467,888), XSPR_MASK, TITAN, PPCNONE, {RS}}, +{"mtppr", XSPR(31,467,896), XSPR_MASK, POWER7, PPCNONE, {RS}}, +{"mtppr32", XSPR(31,467,898), XSPR_MASK, POWER7, PPCNONE, {RS}}, {"mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, PPCNONE, {RS}}, {"mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, PPCNONE, {RS}}, {"mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, PPCNONE, {RS}}, -- cgit v1.1