From 07a28fab1145a0c0fa124b737d3956fbe5c43e5e Mon Sep 17 00:00:00 2001 From: Nick Clifton Date: Wed, 9 Dec 2009 08:38:04 +0000 Subject: PR 10924 * arm-dis.c (print_insn_arm): Mark insns that use the PC in post-indexed addressing as unpredictable. --- opcodes/ChangeLog | 6 ++++++ opcodes/arm-dis.c | 16 +++++++++++----- 2 files changed, 17 insertions(+), 5 deletions(-) (limited to 'opcodes') diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 7ecb512..9e2dfbd 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,9 @@ +2009-12-09 Nick Clifton + + PR 10924 + * arm-dis.c (print_insn_arm): Mark insns that use the PC in + post-indexed addressing as unpredictable. + 2009-12-03 H.J. Lu * i386-dis.c (FXSAVE_Fixup): New. diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index a871d23..3bfad52 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -2931,11 +2931,17 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) NEGATIVE_BIT_SET ? "-" : "", arm_regnames[given & 0xf]); - /* Writeback is automatically implied by post- addressing. - Setting the W bit is unnecessary and ARM specify it as - being unpredictable. */ - if (WRITEBACK_BIT_SET && ! allow_unpredictable) - func (stream, UNPREDICTABLE_INSTRUCTION); + if (! allow_unpredictable) + { + /* Writeback is automatically implied by post- addressing. + Setting the W bit is unnecessary and ARM specify it as + being unpredictable. */ + if (WRITEBACK_BIT_SET + /* Specifying the PC register as the post-indexed + registers is also unpredictable. */ + || ((given & 0xf) == 0xf)) + func (stream, UNPREDICTABLE_INSTRUCTION); + } } } break; -- cgit v1.1