From 8ec5cf65a8213988a9f861e6a94d12311e9b04c3 Mon Sep 17 00:00:00 2001 From: Alexis Deruell Date: Fri, 27 Jan 2017 12:00:55 +0000 Subject: Fix disassembling of TIC6X parallel instructions where the previous fetch packet ended with a 32-bit insn. PR 21056 opcodes * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel instructions when the previous fetch packet ends with a 32-bit instruction. gas * testsuite/gas/tic6x/insns16-parallel.s: New test case. * testsuite/gas/tic6x/insns16-parallel.d: New test driver. --- opcodes/tic6x-dis.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) (limited to 'opcodes/tic6x-dis.c') diff --git a/opcodes/tic6x-dis.c b/opcodes/tic6x-dis.c index d94d662..1a6f575 100644 --- a/opcodes/tic6x-dis.c +++ b/opcodes/tic6x-dis.c @@ -510,8 +510,17 @@ print_insn_tic6x (bfd_vma addr, struct disassemble_info *info) prev_header_based = tic6x_check_fetch_packet_header (fp_prev, &prev_header, info); - if (prev_header_based && prev_header.word_compact[6]) - p_bit = prev_header.p_bits[13]; + if (prev_header_based) + { + if (prev_header.word_compact[6]) + p_bit = prev_header.p_bits[13]; + else + { + unsigned int prev_opcode = tic6x_extract_32 (fp_prev + 24, + info); + p_bit = (prev_opcode & 0x1) ? TRUE : FALSE; + } + } else { unsigned int prev_opcode = tic6x_extract_32 (fp_prev + 28, -- cgit v1.1