From 0c115f8483ac32dc95fde902cac8c8bb99f9c3be Mon Sep 17 00:00:00 2001 From: Alan Modra Date: Thu, 30 Jan 2020 21:59:20 +1030 Subject: ubsan: m32c: left shift of negative value More nonsense fixing "bugs" with left shifts of signed values. Yes, the C standard does say this is undefined (and right shifts of signed values are implementation defined BTW) but in practice there is no problem with current machines. 1's complement is a thing of the past. cpu/ * m32c.cpu (f-src32-rn-unprefixed-QI): Shift before inverting. (f-src32-rn-prefixed-QI, f-dst32-rn-unprefixed-QI): Likewise. (f-dst32-rn-prefixed-QI): Likewise. (f-dsp-32-s32): Mask before shifting left. (f-dsp-48-u32, f-dsp-48-s32): Likewise. (f-bitbase32-16-s11-unprefixed): Multiply signed field rather than shifting left. (f-bitbase32-24-s11-prefixed, f-bitbase32-24-s19-prefixed): Likewise. (h-gr-SI): Mask before shifting. opcodes/ * m32c-ibld.c: Regenerate. --- opcodes/m32c-ibld.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) (limited to 'opcodes/m32c-ibld.c') diff --git a/opcodes/m32c-ibld.c b/opcodes/m32c-ibld.c index 976b70b..7083a57 100644 --- a/opcodes/m32c-ibld.c +++ b/opcodes/m32c-ibld.c @@ -609,14 +609,14 @@ m32c_cgen_insert_operand (CGEN_CPU_DESC cd, case M32C_OPERAND_BIT32RNPREFIXED : { long value = fields->f_dst32_rn_prefixed_QI; - value = (((((((~ (value))) << (1))) & (2))) | (((((USI) (value) >> (1))) & (1)))); + value = (((((~ (((value) << (1))))) & (2))) | (((((USI) (value) >> (1))) & (1)))); errmsg = insert_normal (cd, value, 0, 0, 16, 2, 32, total_length, buffer); } break; case M32C_OPERAND_BIT32RNUNPREFIXED : { long value = fields->f_dst32_rn_unprefixed_QI; - value = (((((((~ (value))) << (1))) & (2))) | (((((USI) (value) >> (1))) & (1)))); + value = (((((~ (((value) << (1))))) & (2))) | (((((USI) (value) >> (1))) & (1)))); errmsg = insert_normal (cd, value, 0, 0, 8, 2, 32, total_length, buffer); } break; @@ -1191,7 +1191,7 @@ m32c_cgen_insert_operand (CGEN_CPU_DESC cd, case M32C_OPERAND_DST32RNPREFIXEDQI : { long value = fields->f_dst32_rn_prefixed_QI; - value = (((((((~ (value))) << (1))) & (2))) | (((((USI) (value) >> (1))) & (1)))); + value = (((((~ (((value) << (1))))) & (2))) | (((((USI) (value) >> (1))) & (1)))); errmsg = insert_normal (cd, value, 0, 0, 16, 2, 32, total_length, buffer); } break; @@ -1212,7 +1212,7 @@ m32c_cgen_insert_operand (CGEN_CPU_DESC cd, case M32C_OPERAND_DST32RNUNPREFIXEDQI : { long value = fields->f_dst32_rn_unprefixed_QI; - value = (((((((~ (value))) << (1))) & (2))) | (((((USI) (value) >> (1))) & (1)))); + value = (((((~ (((value) << (1))))) & (2))) | (((((USI) (value) >> (1))) & (1)))); errmsg = insert_normal (cd, value, 0, 0, 8, 2, 32, total_length, buffer); } break; @@ -1317,7 +1317,7 @@ m32c_cgen_insert_operand (CGEN_CPU_DESC cd, case M32C_OPERAND_IMM_32_SI : { long value = fields->f_dsp_32_s32; - value = EXTSISI (((((((((UINT) (value) >> (24))) & (255))) | (((((UINT) (value) >> (8))) & (65280))))) | (((((((value) << (8))) & (16711680))) | (((((value) << (24))) & (0xff000000))))))); + value = EXTSISI (((((((((UINT) (value) >> (24))) & (255))) | (((((UINT) (value) >> (8))) & (65280))))) | (((((((value) & (65280))) << (8))) | (((((value) & (255))) << (24))))))); errmsg = insert_normal (cd, value, 0|(1<f_src32_rn_prefixed_QI; - value = (((((((~ (value))) << (1))) & (2))) | (((((USI) (value) >> (1))) & (1)))); + value = (((((~ (((value) << (1))))) & (2))) | (((((USI) (value) >> (1))) & (1)))); errmsg = insert_normal (cd, value, 0, 0, 18, 2, 32, total_length, buffer); } break; @@ -1624,7 +1624,7 @@ m32c_cgen_insert_operand (CGEN_CPU_DESC cd, case M32C_OPERAND_SRC32RNUNPREFIXEDQI : { long value = fields->f_src32_rn_unprefixed_QI; - value = (((((((~ (value))) << (1))) & (2))) | (((((USI) (value) >> (1))) & (1)))); + value = (((((~ (((value) << (1))))) & (2))) | (((((USI) (value) >> (1))) & (1)))); errmsg = insert_normal (cd, value, 0, 0, 10, 2, 32, total_length, buffer); } break; @@ -1851,7 +1851,7 @@ m32c_cgen_extract_operand (CGEN_CPU_DESC cd, length = extract_normal (cd, ex_info, insn_value, 0|(1<f_dsp_16_s8); if (length <= 0) break; { - FLD (f_bitbase32_16_s11_unprefixed) = ((((FLD (f_dsp_16_s8)) << (3))) | (FLD (f_bitno32_unprefixed))); + FLD (f_bitbase32_16_s11_unprefixed) = ((((FLD (f_dsp_16_s8)) * (8))) | (FLD (f_bitno32_unprefixed))); } } break; @@ -1923,7 +1923,7 @@ m32c_cgen_extract_operand (CGEN_CPU_DESC cd, length = extract_normal (cd, ex_info, insn_value, 0|(1<f_dsp_24_s8); if (length <= 0) break; { - FLD (f_bitbase32_24_s11_prefixed) = ((((FLD (f_dsp_24_s8)) << (3))) | (FLD (f_bitno32_prefixed))); + FLD (f_bitbase32_24_s11_prefixed) = ((((FLD (f_dsp_24_s8)) * (8))) | (FLD (f_bitno32_prefixed))); } } break; @@ -1936,7 +1936,7 @@ m32c_cgen_extract_operand (CGEN_CPU_DESC cd, length = extract_normal (cd, ex_info, insn_value, 0|(1<f_dsp_32_s8); if (length <= 0) break; { - FLD (f_bitbase32_24_s19_prefixed) = ((((FLD (f_dsp_24_u8)) << (3))) | (((((FLD (f_dsp_32_s8)) << (11))) | (FLD (f_bitno32_prefixed))))); + FLD (f_bitbase32_24_s19_prefixed) = ((((FLD (f_dsp_24_u8)) << (3))) | (((((FLD (f_dsp_32_s8)) * (2048))) | (FLD (f_bitno32_prefixed))))); } } break; @@ -2480,7 +2480,7 @@ m32c_cgen_extract_operand (CGEN_CPU_DESC cd, { long value; length = extract_normal (cd, ex_info, insn_value, 0|(1<> (24))) & (255))) | (((((UINT) (value) >> (8))) & (65280))))) | (((((((value) << (8))) & (16711680))) | (((((value) << (24))) & (0xff000000))))))); + value = EXTSISI (((((((((UINT) (value) >> (24))) & (255))) | (((((UINT) (value) >> (8))) & (65280))))) | (((((((value) & (65280))) << (8))) | (((((value) & (255))) << (24))))))); fields->f_dsp_32_s32 = value; } break; @@ -2539,7 +2539,7 @@ m32c_cgen_extract_operand (CGEN_CPU_DESC cd, } if (length <= 0) break; { - FLD (f_dsp_48_s32) = ((((FLD (f_dsp_48_u16)) & (65535))) | (((((FLD (f_dsp_64_u16)) << (16))) & (0xffff0000)))); + FLD (f_dsp_48_s32) = ((((FLD (f_dsp_48_u16)) & (65535))) | (((((FLD (f_dsp_64_u16)) & (65535))) << (16)))); } } break; -- cgit v1.1