From 57b64c4103ffeadd524eb80b4a7d61be8c8ec871 Mon Sep 17 00:00:00 2001 From: Egeyar Bagcioglu Date: Mon, 3 Dec 2018 17:31:44 +0000 Subject: [aarch64] - Only use MOV for disassembly when shifter op is LSL #0 ARM Architecture Reference Manual for the profile ARMv8-A, Issue C.a, states that MOV (register) is an alias of the ORR (shifted register) iff shift == '00' && imm6 == '000000' && Rn == '11111'. However, mov is currently preferred for a broader range of orr instructions, which is incorrect. 2018-12-03 Egeyar Bagcioglu opcodes: PR 23193 PR 19721 * aarch64-tbl.h (aarch64_opcode_table): Only disassemble an ORR encoding as MOV if the shift operation is a left shift of zero. gas: PR 23193 PR 19721 * testsuite/gas/aarch64/pr19721.s: Add new test cases. * testsuite/gas/aarch64/pr19721.d: Correct existing test cases and add new ones. --- opcodes/aarch64-tbl.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'opcodes/aarch64-tbl.h') diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 6fb74bf..0ba72cb 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -3369,7 +3369,7 @@ struct aarch64_opcode aarch64_opcode_table[] = CORE_INSN ("and", 0xa000000, 0x7f200000, log_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF), CORE_INSN ("bic", 0xa200000, 0x7f200000, log_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF), CORE_INSN ("orr", 0x2a000000, 0x7f200000, log_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF), - CORE_INSN ("mov", 0x2a0003e0, 0x7f2003e0, log_shift, 0, OP2 (Rd, Rm_SFT), QL_I2SAMER, F_ALIAS | F_SF), + CORE_INSN ("mov", 0x2a0003e0, 0x7fe0ffe0, log_shift, 0, OP2 (Rd, Rm_SFT), QL_I2SAMER, F_ALIAS | F_SF), CORE_INSN ("uxtw", 0x2a0003e0, 0x7f2003e0, log_shift, OP_UXTW, OP2 (Rd, Rm), QL_I2SAMEW, F_ALIAS | F_PSEUDO), CORE_INSN ("orn", 0x2a200000, 0x7f200000, log_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF), CORE_INSN ("mvn", 0x2a2003e0, 0x7f2003e0, log_shift, 0, OP2 (Rd, Rm_SFT), QL_I2SAMER, F_ALIAS | F_SF), -- cgit v1.1