From 01c1ee4a70478178eb37e46692a02fb846a2f77b Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Tue, 2 Jul 2019 10:52:16 +0100 Subject: [AArch64] Allow MOVPRFX to be used with FMOV The entry for the FMOV alias of FCPY was missing C_SCAN_MOVPRFX. (The entry for FCPY itself was OK.) This was the only /m-predicated instruction I could see that was missing the flag. 2019-07-02 Richard Sandiford opcodes/ * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the SVE FMOV alias of FCPY. gas/ * testsuite/gas/aarch64/sve-movprfx_27.s, * testsuite/gas/aarch64/sve-movprfx_27.d: New test. --- opcodes/aarch64-tbl.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'opcodes/aarch64-tbl.h') diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 6216750..ee36f1c 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -3809,7 +3809,7 @@ struct aarch64_opcode aarch64_opcode_table[] = CORE_INSN ("ble", 0x5400000d, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), /* SVE instructions. */ _SVE_INSN ("fmov", 0x2539c000, 0xff3fe000, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_FPIMM8), OP_SVE_VU_HSD, F_ALIAS, 0), - _SVE_INSN ("fmov", 0x0510c000, 0xff30e000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg4_16, SVE_FPIMM8), OP_SVE_VMU_HSD, F_ALIAS, 0), + _SVE_INSNC ("fmov", 0x0510c000, 0xff30e000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg4_16, SVE_FPIMM8), OP_SVE_VMU_HSD, F_ALIAS, C_SCAN_MOVPRFX, 0), _SVE_INSN ("mov", 0x04603000, 0xffe0fc00, sve_misc, OP_MOV_Z_Z, OP2 (SVE_Zd, SVE_Zn), OP_SVE_DD, F_ALIAS | F_MISC, 0), _SVE_INSN ("mov", 0x05202000, 0xff20fc00, sve_index, OP_MOV_Z_V, OP2 (SVE_Zd, SVE_VZn), OP_SVE_VV_BHSDQ, F_ALIAS | F_MISC, 0), _SVE_INSN ("mov", 0x05203800, 0xff3ffc00, sve_size_bhsd, 0, OP2 (SVE_Zd, Rn_SP), OP_SVE_VR_BHSD, F_ALIAS, 0), -- cgit v1.1