From 3fd229a447cd28a70bfd921f617bc6c3553b8fdd Mon Sep 17 00:00:00 2001 From: Sudakshina Das Date: Wed, 26 Sep 2018 10:54:07 +0100 Subject: [PATCH, BINUTILS, AARCH64, 5/9] Add DC CVADP instruction This patch is part of the patch series to add support for ARMv8.5-A extensions. (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order/dc-data-cache-operation-an-alias-of-sys) This patch adds the DC CVADP instruction. Since this has a separate identification mechanism a new feature bit is added. *** include/ChangeLog *** 2018-10-09 Sudakshina Das * opcode/aarch64.h (AARCH64_FEATURE_CVADP): New. *** opcodes/ChangeLog *** 2018-10-09 Sudakshina Das * aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp. (aarch64_sys_ins_reg_supported_p): New check for above. *** gas/ChangeLog *** 2018-10-09 Sudakshina Das * testsuite/gas/aarch64/sysreg-4.s: Test instruction. * testsuite/gas/aarch64/sysreg-4.d: Likewise. * testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise. --- opcodes/aarch64-opc.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'opcodes/aarch64-opc.c') diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index f3c436c..9562ba8 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -4349,6 +4349,7 @@ const aarch64_sys_ins_reg aarch64_sys_regs_dc[] = { "csw", CPENS (0, C7, C10, 2), F_HASXT }, { "cvau", CPENS (3, C7, C11, 1), F_HASXT }, { "cvap", CPENS (3, C7, C12, 1), F_HASXT | F_ARCHEXT }, + { "cvadp", CPENS (3, C7, C13, 1), F_HASXT | F_ARCHEXT }, { "civac", CPENS (3, C7, C14, 1), F_HASXT }, { "cisw", CPENS (0, C7, C14, 2), F_HASXT }, { 0, CPENS(0,0,0,0), 0 } @@ -4488,6 +4489,11 @@ aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features, && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2)) return FALSE; + /* DC CVADP. Values are from aarch64_sys_regs_dc. */ + if (reg->value == CPENS (3, C7, C13, 1) + && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_CVADP)) + return FALSE; + /* AT S1E1RP, AT S1E1WP. Values are from aarch64_sys_regs_at. */ if ((reg->value == CPENS (0, C7, C9, 0) || reg->value == CPENS (0, C7, C9, 1)) -- cgit v1.1