From 3dd032c5fb4eb7fc6bc0341d348da5c75e2d8e38 Mon Sep 17 00:00:00 2001
From: Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
Date: Wed, 17 Nov 2021 20:15:13 +0000
Subject: aarch64: [SME] Add SME mode selection and state access instructions

This patch is adding new SME mode selection and state access instructions:
* Add SMSTART and SMSTOP instructions.
* Add SVCR system register.

gas/ChangeLog:

	* config/tc-aarch64.c (parse_sme_sm_za): New parser.
	(parse_operands): New parser.
	* testsuite/gas/aarch64/sme-8-illegal.d: New test.
	* testsuite/gas/aarch64/sme-8-illegal.l: New test.
	* testsuite/gas/aarch64/sme-8-illegal.s: New test.
	* testsuite/gas/aarch64/sme-8.d: New test.
	* testsuite/gas/aarch64/sme-8.s: New test.

include/ChangeLog:

	* opcode/aarch64.h (enum aarch64_opnd): New operand
	AARCH64_OPND_SME_SM_ZA.
	(enum aarch64_insn_class): New instruction classes
	sme_start and sme_stop.

opcodes/ChangeLog:

	* aarch64-asm.c (aarch64_ins_pstatefield): New inserter.
	(aarch64_ins_sme_sm_za): New inserter.
	* aarch64-dis.c (aarch64_ext_imm): New extractor.
	(aarch64_ext_pstatefield): New extractor.
	(aarch64_ext_sme_sm_za): New extractor.
	* aarch64-opc.c (operand_general_constraint_met_p):
	New pstatefield value for SME instructions.
	(aarch64_print_operand): Printout for OPND_SME_SM_ZA.
	(SR_SME): New register SVCR.
	* aarch64-opc.h (F_REG_IN_CRM): New register endcoding.
	* aarch64-opc.h (F_IMM_IN_CRM): New immediate endcoding.
	(PSTATE_ENCODE_CRM): Encode CRm field.
	(PSTATE_DECODE_CRM): Decode CRm field.
	(PSTATE_ENCODE_CRM_IMM): Encode CRm immediate field.
	(PSTATE_DECODE_CRM_IMM): Decode CRm immediate field.
	(PSTATE_ENCODE_CRM_AND_IMM): Encode CRm and immediate
	field.
	* aarch64-tbl.h (struct aarch64_opcode): New SMSTART
	and SMSTOP instructions.
	aarch64-asm-2.c: Regenerate.
	aarch64-dis-2.c: Regenerate.
	aarch64-opc-2.c: Regenerate.
---
 opcodes/aarch64-dis.c | 38 ++++++++++++++++++++++++++++++++++++--
 1 file changed, 36 insertions(+), 2 deletions(-)

(limited to 'opcodes/aarch64-dis.c')

diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index d21c6b0..c2b365a 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -664,7 +664,7 @@ aarch64_ext_shll_imm (const aarch64_operand *self ATTRIBUTE_UNUSED,
 bool
 aarch64_ext_imm (const aarch64_operand *self, aarch64_opnd_info *info,
 		 const aarch64_insn code,
-		 const aarch64_inst *inst ATTRIBUTE_UNUSED,
+		 const aarch64_inst *inst,
 		 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
 {
   uint64_t imm;
@@ -682,6 +682,10 @@ aarch64_ext_imm (const aarch64_operand *self, aarch64_opnd_info *info,
   if (info->type == AARCH64_OPND_ADDR_ADRP)
     imm <<= 12;
 
+  if (inst->operands[0].type == AARCH64_OPND_PSTATEFIELD
+      && inst->operands[0].sysreg.flags & F_IMM_IN_CRM)
+    imm &= PSTATE_DECODE_CRM_IMM (inst->operands[0].sysreg.flags);
+
   info->imm.value = imm;
   return true;
 }
@@ -1226,11 +1230,20 @@ aarch64_ext_pstatefield (const aarch64_operand *self ATTRIBUTE_UNUSED,
 			 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
 {
   int i;
+  aarch64_insn fld_crm = extract_field (FLD_CRm, code, 0);
   /* op1:op2 */
   info->pstatefield = extract_fields (code, 0, 2, FLD_op1, FLD_op2);
   for (i = 0; aarch64_pstatefields[i].name != NULL; ++i)
     if (aarch64_pstatefields[i].value == (aarch64_insn)info->pstatefield)
-      return true;
+      {
+        /* PSTATEFIELD name can be encoded partially in CRm[3:1].  */
+        uint32_t flags = aarch64_pstatefields[i].flags;
+        if ((flags & F_REG_IN_CRM)
+            && ((fld_crm & 0xe) != PSTATE_DECODE_CRM (flags)))
+          continue;
+        info->sysreg.flags = flags;
+        return true;
+      }
   /* Reserved value in <pstatefield>.  */
   return false;
 }
@@ -1856,6 +1869,27 @@ aarch64_ext_sme_addr_ri_u4xvl (const aarch64_operand *self,
   return true;
 }
 
+/* Decode {SM|ZA} filed for SMSTART and SMSTOP instructions.  */
+bool
+aarch64_ext_sme_sm_za (const aarch64_operand *self,
+                       aarch64_opnd_info *info, aarch64_insn code,
+                       const aarch64_inst *inst ATTRIBUTE_UNUSED,
+                       aarch64_operand_error *errors ATTRIBUTE_UNUSED)
+{
+  info->pstatefield = 0x1b;
+  aarch64_insn fld_crm = extract_field (self->fields[0], code, 0);
+  fld_crm >>= 1;    /* CRm[3:1].  */
+
+  if (fld_crm == 0x1)
+    info->reg.regno = 's';
+  else if (fld_crm == 0x2)
+    info->reg.regno = 'z';
+  else
+    assert (0);
+
+  return true;
+}
+
 /* Decode Zn[MM], where MM has a 7-bit triangular encoding.  The fields
    array specifies which field to use for Zn.  MM is encoded in the
    concatenation of imm5 and SVE_tszh, with imm5 being the less
-- 
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