From a9e2cefdf00202e0ba59825bd66a01ec41ac3ed0 Mon Sep 17 00:00:00 2001 From: Victor Do Nascimento Date: Wed, 15 Nov 2023 17:21:39 +0000 Subject: aarch64: Implement TLBIP 128-bit instruction The addition of 128-bit page table descriptors and, with it, the addition of 128-bit system registers for these means that special "invalidate translation table entry" instructions are needed to cope with the new 128-bit model. This is introduced with the `tlbpi' instruction, implemented here. --- include/opcode/aarch64.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/opcode') diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index b81475f..768caec 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -566,6 +566,7 @@ enum aarch64_opnd AARCH64_OPND_SYSREG_DC, /* System register operand. */ AARCH64_OPND_SYSREG_IC, /* System register operand. */ AARCH64_OPND_SYSREG_TLBI, /* System register operand. */ + AARCH64_OPND_SYSREG_TLBIP, /* System register operand. */ AARCH64_OPND_SYSREG_SR, /* System register RCTX operand. */ AARCH64_OPND_BARRIER, /* Barrier operand. */ AARCH64_OPND_BARRIER_DSB_NXS, /* Barrier operand for DSB nXS variant. */ -- cgit v1.1