From 8bea934667cdf3046dd388e9d07ca055d4ff5277 Mon Sep 17 00:00:00 2001 From: Lulu Cai Date: Sat, 13 Dec 2025 15:33:15 +0800 Subject: LoongArch: Add disassembly support for ud ui5 ud ui5, also known as amswap.w rd,$r1,rj(rd==rj), is displayed as "ud ui5" by default during disassembly. Alternatively, the original instruction can be printed using the objdump -M no-aliases. To implement this support, a format specifier "ru0:5,ru5:5" for ud is applied exclusively during disassembly. This specifier indicates that registers should be printed using their corresponding numeric values, and when the instruction is identified as ud, only a single parameter is displayed. binutils/ * testsuite/binutils-all/loongarch64/dis-amswap-ud-noaliases.d: New test. * testsuite/binutils-all/loongarch64/dis-amswap-ud.d: New test. * testsuite/binutils-all/loongarch64/dis-amswap-ud.s: New test. gas/ * testsuite/gas/loongarch/macro_ud.d: Update test. include/ * opcode/loongarch.h: New macro. opcodes/ * loongarch-dis.c (get_loongarch_opcode_by_binfmt): Correct match `ud`. (dis_one_arg): Disassemble the `ud` parameter. * loongarch-opc.c: Add opcode for "ud" alias. --- include/opcode/loongarch.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/opcode') diff --git a/include/opcode/loongarch.h b/include/opcode/loongarch.h index fb6f8be68de..3e8a90a2b27 100644 --- a/include/opcode/loongarch.h +++ b/include/opcode/loongarch.h @@ -116,6 +116,7 @@ extern "C" #define LARCH_RD_RJ_A0 0x084 #define LARCH_GET_RD(insn) (insn & 0x1f) #define LARCH_GET_RJ(insn) ((insn >> 5) & 0x1f) + #define LARCH_GET_RK(insn) ((insn >> 10) & 0x1f) typedef uint32_t insn_t; -- cgit v1.2.3