From 04b4939b0362686e7b3ebb531edb0bbd37a59a1b Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Tue, 16 Jun 2015 21:29:48 +0545 Subject: gdb: riscv: enable sim integration Now the simulator can be loaded via gdb using "target sim". --- include/gdb/ChangeLog | 4 ++ include/gdb/sim-riscv.h | 99 +++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 103 insertions(+) create mode 100644 include/gdb/sim-riscv.h (limited to 'include/gdb') diff --git a/include/gdb/ChangeLog b/include/gdb/ChangeLog index 27efbaf..32a0928 100644 --- a/include/gdb/ChangeLog +++ b/include/gdb/ChangeLog @@ -1,3 +1,7 @@ +2021-02-04 Mike Frysinger + + * sim-riscv.h: New file. + 2021-01-07 Mike Frysinger * remote-sim.h (sim_memory_map): Define. diff --git a/include/gdb/sim-riscv.h b/include/gdb/sim-riscv.h new file mode 100644 index 0000000..23e5f76 --- /dev/null +++ b/include/gdb/sim-riscv.h @@ -0,0 +1,99 @@ +/* This file defines the interface between the RISC-V simulator and GDB. + + Copyright (C) 2005-2021 Free Software Foundation, Inc. + Contributed by Mike Frysinger. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +/* Order has to match gdb riscv-tdep list. */ +enum sim_riscv_regnum { + SIM_RISCV_ZERO_REGNUM = 0, + SIM_RISCV_RA_REGNUM, + SIM_RISCV_SP_REGNUM, + SIM_RISCV_GP_REGNUM, + SIM_RISCV_TP_REGNUM, + SIM_RISCV_T0_REGNUM, + SIM_RISCV_T1_REGNUM, + SIM_RISCV_T2_REGNUM, + SIM_RISCV_S0_REGNUM, +#define SIM_RISCV_FP_REGNUM SIM_RISCV_S0_REGNUM + SIM_RISCV_S1_REGNUM, + SIM_RISCV_A0_REGNUM, + SIM_RISCV_A1_REGNUM, + SIM_RISCV_A2_REGNUM, + SIM_RISCV_A3_REGNUM, + SIM_RISCV_A4_REGNUM, + SIM_RISCV_A5_REGNUM, + SIM_RISCV_A6_REGNUM, + SIM_RISCV_A7_REGNUM, + SIM_RISCV_S2_REGNUM, + SIM_RISCV_S3_REGNUM, + SIM_RISCV_S4_REGNUM, + SIM_RISCV_S5_REGNUM, + SIM_RISCV_S6_REGNUM, + SIM_RISCV_S7_REGNUM, + SIM_RISCV_S8_REGNUM, + SIM_RISCV_S9_REGNUM, + SIM_RISCV_S10_REGNUM, + SIM_RISCV_S11_REGNUM, + SIM_RISCV_T3_REGNUM, + SIM_RISCV_T4_REGNUM, + SIM_RISCV_T5_REGNUM, + SIM_RISCV_T6_REGNUM, + SIM_RISCV_PC_REGNUM, + SIM_RISCV_FT0_REGNUM, +#define SIM_RISCV_FIRST_FP_REGNUM SIM_RISCV_FT0_REGNUM + SIM_RISCV_FT1_REGNUM, + SIM_RISCV_FT2_REGNUM, + SIM_RISCV_FT3_REGNUM, + SIM_RISCV_FT4_REGNUM, + SIM_RISCV_FT5_REGNUM, + SIM_RISCV_FT6_REGNUM, + SIM_RISCV_FT7_REGNUM, + SIM_RISCV_FS0_REGNUM, + SIM_RISCV_FS1_REGNUM, + SIM_RISCV_FA0_REGNUM, + SIM_RISCV_FA1_REGNUM, + SIM_RISCV_FA2_REGNUM, + SIM_RISCV_FA3_REGNUM, + SIM_RISCV_FA4_REGNUM, + SIM_RISCV_FA5_REGNUM, + SIM_RISCV_FA6_REGNUM, + SIM_RISCV_FA7_REGNUM, + SIM_RISCV_FS2_REGNUM, + SIM_RISCV_FS3_REGNUM, + SIM_RISCV_FS4_REGNUM, + SIM_RISCV_FS5_REGNUM, + SIM_RISCV_FS6_REGNUM, + SIM_RISCV_FS7_REGNUM, + SIM_RISCV_FS8_REGNUM, + SIM_RISCV_FS9_REGNUM, + SIM_RISCV_FS10_REGNUM, + SIM_RISCV_FS11_REGNUM, + SIM_RISCV_FT8_REGNUM, + SIM_RISCV_FT9_REGNUM, + SIM_RISCV_FT10_REGNUM, + SIM_RISCV_FT11_REGNUM, +#define SIM_RISCV_LAST_FP_REGNUM SIM_RISCV_FT11_REGNUM + +#define SIM_RISCV_FIRST_CSR_REGNUM SIM_RISCV_LAST_FP_REGNUM + 1 +#define DECLARE_CSR(name, num, ...) SIM_RISCV_ ## num ## _REGNUM, +#include "opcode/riscv-opc.h" +#undef DECLARE_CSR +#define SIM_RISCV_LAST_CSR_REGNUM SIM_RISCV_LAST_REGNUM - 1 + + SIM_RISCV_LAST_REGNUM +}; -- cgit v1.1