From 4f46c0bc36471b725de0253bfec1a42a36e2c5c5 Mon Sep 17 00:00:00 2001 From: Andrew Burgess Date: Mon, 4 Jul 2022 17:45:25 +0100 Subject: opcodes: add new sub-mnemonic disassembler style When adding libopcodes disassembler styling support for AArch64, it feels like the results would be improved by having a new sub-mnemonic style. This will be used in cases like: add w16, w7, w1, uxtb #2 ^^^^----- Here And: cinc w0, w1, ne ^^----- Here This commit just adds the new style, and prepares objdump to handle the style. A later commit will add AArch64 styling, and will actually make use of the style. As this style is currently unused, there should be no user visible changes after this commit. --- include/dis-asm.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'include/dis-asm.h') diff --git a/include/dis-asm.h b/include/dis-asm.h index 4f91df1..f1a83dc 100644 --- a/include/dis-asm.h +++ b/include/dis-asm.h @@ -62,6 +62,13 @@ enum disassembler_style instructions. */ dis_style_mnemonic, + /* Some architectures include additional mnemonic like fields within the + instruction operands, e.g. on aarch64 'add w16, w7, w1, lsl #2' where + the 'lsl' is an additional piece of text that describes how the + instruction should behave. This sub-mnemonic style can be used for + these pieces of text. */ + dis_style_sub_mnemonic, + /* For things that aren't real machine instructions, but rather assembler directives, e.g. .byte, etc. */ dis_style_assembler_directive, -- cgit v1.1