From 23cedd1dc90d05c4b80d4a4b000ed5f37b9c3268 Mon Sep 17 00:00:00 2001 From: Alan Modra Date: Mon, 9 Apr 2018 09:25:10 +0930 Subject: PowerPC inline PLT call support In addition to the existing relocs we need two more to mark all instructions in the call sequence, PLTCALL on the call itself (plus the toc restore insn for ppc64), and PLTSEQ on others. All relocations in a particular sequence have the same symbol. Example ppc64 ELFv2 assembly: .reloc .,R_PPC64_PLTSEQ,puts std 2,24(1) addis 12,2,puts@plt@ha # .reloc .,R_PPC64_PLT16_HA,puts ld 12,puts@plt@l(12) # .reloc .,R_PPC64_PLT16_LO_DS,puts .reloc .,R_PPC64_PLTSEQ,puts mtctr 12 .reloc .,R_PPC64_PLTCALL,puts bctrl ld 2,24(1) Example ppc32 -fPIC assembly: addis 12,30,puts+32768@plt@ha # .reloc .,R_PPC_PLT16_HA,puts+0x8000 lwz 12,12,puts+32768@plt@l # .reloc .,R_PPC_PLT16_LO,puts+0x8000 .reloc .,R_PPC_PLTSEQ,puts+32768 mtctr 12 .reloc .,R_PPC_PLTCALL,puts+32768 bctrl Marking sequences like this allows the linker to convert them to nops and a direct call if the target symbol turns out to be local. When the call is __tls_get_addr, each relocation shown above is paired with an R_PPC*_TLSLD or R_PPC*_TLSGD reloc to additionally mark the sequence for possible TLS optimization. The TLSLD or TLSGD relocs are emitted first. include/ * elf/ppc.h (R_PPC_PLTSEQ, R_PPC_PLTCALL): Define. * elf/ppc64.h (R_PPC64_PLTSEQ, R_PPC64_PLTCALL): Define. bfd/ * elf32-ppc.c (ppc_elf_howto_raw): Add PLTSEQ and PLTCALL howtos. (is_plt_seq_reloc): New function. (ppc_elf_check_relocs): Handle PLTSEQ and PLTCALL relocs. (ppc_elf_tls_optimize): Handle inline plt call sequence. (ppc_elf_relax_section): Handle PLTCALL reloc. (ppc_elf_relocate_section): Nop out inline plt call sequence when resolving locally. * elf64-ppc.c (ppc64_elf_howto_raw): Add R_PPC64_PLTSEQ and R_PPC64_PLTCALL entries. Comment R_PPC64_TOCSAVE. (has_tls_get_addr_call): Correct comment. (is_branch_reloc): Add PLTCALL. (is_plt_seq_reloc): New function. (ppc64_elf_check_relocs): Handle PLT16_LO_DS reloc. Set has_tls_reloc for R_PPC64_TLSGD and R_PPC64_TLSLD. Create plt entry for R_PPC64_PLTCALL. (ppc64_elf_tls_optimize): Handle inline plt call sequence. (ppc_type_of_stub): Handle PLTCALL reloc. (toc_adjusting_stub_needed): Likewise. (ppc64_elf_relocate_section): Set "can_plt_call" for PLTCALL reloc insn. Nop out inline plt call sequence when resolving locally. Handle __tls_get_addr inline plt call optimization. elfcpp/ * powerpc.h (R_POWERPC_PLTSEQ, R_POWERPC_PLTCALL): Define. gold/ * powerpc.cc (Target_powerpc::Track_tls::maybe_skip_tls_get_addr_call): Handle inline plt sequence relocs. (Stub_table::Plt_stub_key::Plt_stub_key): Likewise. (Target_powerpc::Scan::reloc_needs_plt_for_ifunc): Likewise. (Target_powerpc::Relocate::relocate): Likewise. --- gold/powerpc.cc | 65 ++++++++++++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 57 insertions(+), 8 deletions(-) (limited to 'gold/powerpc.cc') diff --git a/gold/powerpc.cc b/gold/powerpc.cc index c3f1b23..314eaa7 100644 --- a/gold/powerpc.cc +++ b/gold/powerpc.cc @@ -78,8 +78,10 @@ struct Stub_table_owner const Output_section::Input_section* owner; }; -inline bool -is_branch_reloc(unsigned int r_type); +inline bool is_branch_reloc(unsigned int); + +template +inline bool is_plt16_reloc(unsigned int); // Counter incremented on every Powerpc_relobj constructed. static uint32_t object_id = 0; @@ -1211,7 +1213,10 @@ class Target_powerpc : public Sized_target unsigned int r_type, const Symbol* gsym) { bool is_tls_call = ((r_type == elfcpp::R_POWERPC_REL24 - || r_type == elfcpp::R_PPC_PLTREL24) + || r_type == elfcpp::R_PPC_PLTREL24 + || is_plt16_reloc(r_type) + || r_type == elfcpp::R_POWERPC_PLTSEQ + || r_type == elfcpp::R_POWERPC_PLTCALL) && gsym != NULL && (gsym == target->tls_get_addr() || gsym == target->tls_get_addr_opt())); @@ -4651,7 +4656,8 @@ class Stub_table : public Output_relaxed_input_section if (size != 32) this->addend_ = addend; else if (parameters->options().output_is_position_independent() - && r_type == elfcpp::R_PPC_PLTREL24) + && (r_type == elfcpp::R_PPC_PLTREL24 + || r_type == elfcpp::R_POWERPC_PLTCALL)) { this->addend_ = addend; if (this->addend_ >= 32768) @@ -4668,7 +4674,8 @@ class Stub_table : public Output_relaxed_input_section if (size != 32) this->addend_ = addend; else if (parameters->options().output_is_position_independent() - && r_type == elfcpp::R_PPC_PLTREL24) + && (r_type == elfcpp::R_PPC_PLTREL24 + || r_type == elfcpp::R_POWERPC_PLTCALL)) this->addend_ = addend; } @@ -6569,6 +6576,8 @@ Target_powerpc::Scan::reloc_needs_plt_for_ifunc( case elfcpp::R_POWERPC_PLT16_HI: case elfcpp::R_POWERPC_PLT16_HA: case elfcpp::R_PPC64_PLT16_LO_DS: + case elfcpp::R_POWERPC_PLTSEQ: + case elfcpp::R_POWERPC_PLTCALL: return true; break; @@ -6706,6 +6715,8 @@ Target_powerpc::Scan::local( case elfcpp::R_POWERPC_GNU_VTENTRY: case elfcpp::R_POWERPC_TLS: case elfcpp::R_PPC64_ENTRY: + case elfcpp::R_POWERPC_PLTSEQ: + case elfcpp::R_POWERPC_PLTCALL: break; case elfcpp::R_PPC64_TOC: @@ -7266,6 +7277,8 @@ Target_powerpc::Scan::global( case elfcpp::R_PPC_LOCAL24PC: case elfcpp::R_POWERPC_TLS: case elfcpp::R_PPC64_ENTRY: + case elfcpp::R_POWERPC_PLTSEQ: + case elfcpp::R_POWERPC_PLTCALL: break; case elfcpp::R_PPC64_TOC: @@ -8495,6 +8508,10 @@ Target_powerpc::Relocate::relocate( Address address, section_size_type view_size) { + typedef Powerpc_relocate_functions Reloc; + typedef typename elfcpp::Swap<32, big_endian>::Valtype Insn; + typedef typename elfcpp::Rela Reltype; + if (view == NULL) return true; @@ -8513,14 +8530,22 @@ Target_powerpc::Relocate::relocate( // We have already complained. break; case Track_tls::SKIP: + if (is_plt16_reloc(r_type) + || r_type == elfcpp::R_POWERPC_PLTSEQ) + { + Insn* iview = reinterpret_cast(view); + elfcpp::Swap<32, big_endian>::writeval(iview, nop); + } + else if (size == 64 && r_type == elfcpp::R_POWERPC_PLTCALL) + { + Insn* iview = reinterpret_cast(view); + elfcpp::Swap<32, big_endian>::writeval(iview + 1, nop); + } return true; case Track_tls::NORMAL: break; } - typedef Powerpc_relocate_functions Reloc; - typedef typename elfcpp::Swap<32, big_endian>::Valtype Insn; - typedef typename elfcpp::Rela Reltype; // Offset from start of insn to d-field reloc. const int d_offset = big_endian ? 2 : 0; @@ -8536,6 +8561,8 @@ Target_powerpc::Relocate::relocate( : object->local_has_plt_offset(r_sym)); if (has_plt_offset && !is_plt16_reloc(r_type) + && r_type != elfcpp::R_POWERPC_PLTSEQ + && r_type != elfcpp::R_POWERPC_PLTCALL && (!psymval->is_ifunc_symbol() || Scan::reloc_needs_plt_for_ifunc(target, object, r_type, false))) { @@ -8633,6 +8660,14 @@ Target_powerpc::Relocate::relocate( + target->got_section()->g_o_t()); } } + else if (!has_plt_offset + && (is_plt16_reloc(r_type) + || r_type == elfcpp::R_POWERPC_PLTSEQ)) + { + Insn* iview = reinterpret_cast(view); + elfcpp::Swap<32, big_endian>::writeval(iview, nop); + r_type = elfcpp::R_POWERPC_NONE; + } else if (r_type == elfcpp::R_POWERPC_GOT16 || r_type == elfcpp::R_POWERPC_GOT16_LO || r_type == elfcpp::R_POWERPC_GOT16_HI @@ -8969,6 +9004,18 @@ Target_powerpc::Relocate::relocate( } else if (!has_stub_value) { + if (!has_plt_offset && r_type == elfcpp::R_POWERPC_PLTCALL) + { + // PLTCALL without plt entry => convert to direct call + Insn* iview = reinterpret_cast(view); + Insn insn = elfcpp::Swap<32, big_endian>::readval(iview); + insn = (insn & 1) | b; + elfcpp::Swap<32, big_endian>::writeval(iview, insn); + if (size == 32) + r_type = elfcpp::R_PPC_PLTREL24; + else + r_type = elfcpp::R_POWERPC_REL24; + } Address addend = 0; if (!(size == 32 && (r_type == elfcpp::R_PPC_PLTREL24 @@ -9498,6 +9545,8 @@ Target_powerpc::Relocate::relocate( case elfcpp::R_POWERPC_TLS: case elfcpp::R_POWERPC_GNU_VTINHERIT: case elfcpp::R_POWERPC_GNU_VTENTRY: + case elfcpp::R_POWERPC_PLTSEQ: + case elfcpp::R_POWERPC_PLTCALL: break; case elfcpp::R_PPC64_ADDR64: -- cgit v1.1