From 5f814c3b3f9d99ed724cce14c90a02e29776a90a Mon Sep 17 00:00:00 2001 From: Don Lee Date: Thu, 6 Aug 2009 10:28:38 +0000 Subject: * score-tdep.c: Support a new Sunplus CT S+core variant, S+core 3. * score-tdep.h: Ditto. * NEWS: Ditto. * configure.tgt: Test do we have a simulator. * MAINTAINERS: Add myself under target score --- gdb/score-tdep.h | 106 ++++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 105 insertions(+), 1 deletion(-) (limited to 'gdb/score-tdep.h') diff --git a/gdb/score-tdep.h b/gdb/score-tdep.h index 417676d..792f277 100644 --- a/gdb/score-tdep.h +++ b/gdb/score-tdep.h @@ -38,11 +38,115 @@ enum gdb_regnum #define SCORE_A0_REGNUM 4 #define SCORE_A1_REGNUM 5 #define SCORE_REGSIZE 4 -#define SCORE_NUM_REGS 56 +#define SCORE7_NUM_REGS 56 +#define SCORE3_NUM_REGS 50 #define SCORE_BEGIN_ARG_REGNUM 4 #define SCORE_LAST_ARG_REGNUM 7 #define SCORE_INSTLEN 4 #define SCORE16_INSTLEN 2 +/* Forward declarations. */ +struct regset; + +/* Target-dependent structure in gdbarch */ +struct gdbarch_tdep +{ + /* Cached core file helpers. */ + struct regset *gregset; +}; + +/* Linux Core file support (dirty hack) + + S+core Linux register set definition, copy from S+core Linux */ +struct pt_regs { + /* Pad bytes for argument save space on the stack. */ + unsigned long pad0[6]; /* may be 4,MIPS accept 6var,SCore accepts 4 Var--yuchen */ + + /* Saved main processor registers. */ + unsigned long orig_r4; + unsigned long regs[32]; + + /* Other saved registers. */ + unsigned long cel; + unsigned long ceh; + + unsigned long sr0; /*cnt*/ + unsigned long sr1; /*lcr*/ + unsigned long sr2; /*scr*/ + + /* saved cp0 registers */ + unsigned long cp0_epc; + unsigned long cp0_ema; + unsigned long cp0_psr; + unsigned long cp0_ecr; + unsigned long cp0_condition; +}; + +typedef struct pt_regs elf_gregset_t; + +#ifdef WITH_SIM + +#include + +int soc_gh_can_use_watch(int type, int cnt); +int soc_gh_add_watch(unsigned int addr, int len, int type); +int soc_gh_del_watch(unsigned int addr, int len, int type); +int soc_gh_stopped_by_watch(void); +int soc_gh_add_hardbp(unsigned int addr); +int soc_gh_del_hardbp(unsigned int addr); + +int score_target_can_use_watch(int type, int cnt, int ot); +int score_stopped_by_watch(void); +int score_target_insert_watchpoint (CORE_ADDR addr, int len, int type); +int score_target_remove_watchpoint (CORE_ADDR addr, int len, int type); +int score_target_insert_hw_breakpoint (struct gdbarch *gdbarch, struct bp_target_info * bp_tgt); +int score_target_remove_hw_breakpoint (struct gdbarch *gdbarch, struct bp_target_info * bp_tgt); + +#define TARGET_HAS_HARDWARE_WATCHPOINTS + +#ifdef TARGET_CAN_USE_HARDWARE_WATCHPOINT +#undef TARGET_CAN_USE_HARDWARE_WATCHPOINT + +#define TARGET_CAN_USE_HARDWARE_WATCHPOINT(type, cnt, ot) \ + score_target_can_use_watch(type, cnt, ot) +#endif + +#ifdef STOPPED_BY_WATCHPOINT +#undef STOPPED_BY_WATCHPOINT + +#define STOPPED_BY_WATCHPOINT(w) \ + score_stopped_by_watch() +#endif + +#ifdef target_insert_watchpoint +#undef target_insert_watchpoint + +#define target_insert_watchpoint(addr, len, type) \ + score_target_insert_watchpoint (addr, len, type) +#endif + +#ifdef target_remove_watchpoint +#undef target_remove_watchpoint + +#define target_remove_watchpoint(addr, len, type) \ + score_target_remove_watchpoint (addr, len, type) +#endif + +#ifdef target_insert_hw_breakpoint +#undef target_insert_hw_breakpoint + +#define target_insert_hw_breakpoint(gdbarch, bp_tgt) \ + score_target_insert_hw_breakpoint (gdbarch, bp_tgt) +#endif + +#ifdef target_remove_hw_breakpoint +#undef target_remove_hw_breakpoint + +#define target_remove_hw_breakpoint(gdbarch, bp_tgt) \ + score_target_remove_hw_breakpoint (gdbarch, bp_tgt) +#endif + +#endif /* WITH_SIM */ + #endif /* SCORE_TDEP_H */ -- cgit v1.1