From f4950f76fa56bd60314f05620c39fb31e96bb088 Mon Sep 17 00:00:00 2001 From: Jan Beulich Date: Fri, 3 Jan 2020 10:12:49 +0100 Subject: Arm64: correct 64-bit element fmmla encoding There's just one bit of difference to the 32-bit element form, as per the documentation. --- gas/ChangeLog | 5 +++++ gas/testsuite/gas/aarch64/f64mm.d | 4 ++-- gas/testsuite/gas/aarch64/sve-movprfx-mm.d | 2 +- 3 files changed, 8 insertions(+), 3 deletions(-) (limited to 'gas') diff --git a/gas/ChangeLog b/gas/ChangeLog index 86134cb..933c17e 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,8 @@ +2020-01-03 Jan Beulich + + * testsuite/gas/aarch64/f64mm.d, + testsuite/gas/aarch64/sve-movprfx-mm.d: Adjust expectations. + 2020-01-02 Sergey Belyashov * config/tc-z80.c: Add new architectures: Z180 and eZ80. Add diff --git a/gas/testsuite/gas/aarch64/f64mm.d b/gas/testsuite/gas/aarch64/f64mm.d index a09179a..b2aa861 100644 --- a/gas/testsuite/gas/aarch64/f64mm.d +++ b/gas/testsuite/gas/aarch64/f64mm.d @@ -6,8 +6,8 @@ Disassembly of section \.text: 0+ <\.text>: - *[0-9a-f]+: 64dbe6b1 fmmla z17\.d, z21\.d, z27\.d - *[0-9a-f]+: 64c0e400 fmmla z0\.d, z0\.d, z0\.d + *[0-9a-f]+: 64fbe6b1 fmmla z17\.d, z21\.d, z27\.d + *[0-9a-f]+: 64e0e400 fmmla z0\.d, z0\.d, z0\.d *[0-9a-f]+: a43b17f1 ld1rob {z17\.b}, p5/z, \[sp, x27\] *[0-9a-f]+: a42003e0 ld1rob {z0\.b}, p0/z, \[sp, x0\] *[0-9a-f]+: a4bb17f1 ld1roh {z17\.h}, p5/z, \[sp, x27\] diff --git a/gas/testsuite/gas/aarch64/sve-movprfx-mm.d b/gas/testsuite/gas/aarch64/sve-movprfx-mm.d index 88415ef..f2b480d 100644 --- a/gas/testsuite/gas/aarch64/sve-movprfx-mm.d +++ b/gas/testsuite/gas/aarch64/sve-movprfx-mm.d @@ -21,4 +21,4 @@ Disassembly of section \.text: *[0-9a-f]+: 0420bc11 movprfx z17, z0 *[0-9a-f]+: 64bbe6b1 fmmla z17\.s, z21\.s, z27\.s *[0-9a-f]+: 0420bc11 movprfx z17, z0 - *[0-9a-f]+: 64dbe6b1 fmmla z17\.d, z21\.d, z27\.d + *[0-9a-f]+: 64fbe6b1 fmmla z17\.d, z21\.d, z27\.d -- cgit v1.1