From 1c1e0fe58b9389bd40f5f642d20dc2e1befd4541 Mon Sep 17 00:00:00 2001 From: Srinath Parvathaneni Date: Fri, 30 Aug 2019 10:44:18 +0100 Subject: [PATCH][ARM][GAS]: Assembler support to interpret MVE VMOV instruction correctly. This patch make changes to the assembler to encode MVE VMOV instruction "a" same as "b". a: VMOV
, b: VMOV.F64
, gas/ChangeLog: 2019-08-30 Srinath Parvathaneni * config/tc-arm.c (do_neon_mov): Modify "if" statement. * testsuite/gas/arm/mve-vmov-bad-3.d: New test. * testsuite/gas/arm/mve-vmov-bad-3.l: Likewise. * testsuite/gas/arm/mve-vmov-bad-3.s: Likewise. --- gas/config/tc-arm.c | 8 ++++- gas/testsuite/gas/arm/mve-vmov-1.d | 72 ++++++++++++++++++++++++++++++++++++++ gas/testsuite/gas/arm/mve-vmov-1.s | 7 ++++ 3 files changed, 86 insertions(+), 1 deletion(-) (limited to 'gas') diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index 9a367ca..9273bb5 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -19859,7 +19859,13 @@ do_neon_mov (void) et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); /* It is not an error here if no type is given. */ inst.error = NULL; - if (et.type == NT_float && et.size == 64) + + /* In MVE we interpret the following instructions as same, so ignoring + the following type (float) and size (64) checks. + a: VMOV
, + b: VMOV.F64
, . */ + if ((et.type == NT_float && et.size == 64) + || (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))) { do_vfp_nsyn_opcode ("fcpyd"); break; diff --git a/gas/testsuite/gas/arm/mve-vmov-1.d b/gas/testsuite/gas/arm/mve-vmov-1.d index 504b3e7..de8dabe 100644 --- a/gas/testsuite/gas/arm/mve-vmov-1.d +++ b/gas/testsuite/gas/arm/mve-vmov-1.d @@ -4179,3 +4179,75 @@ Disassembly of section .text: [^>]*> ef24 e154 vmov q7, q2 [^>]*> ef28 e158 vmov q7, q4 [^>]*> ef2e e15e vmov q7, q7 +[^>]*> eeb0 0b40 vmov.f64 d0, d0 +[^>]*> eeb0 0b40 vmov.f64 d0, d0 +[^>]*> eeb0 0b41 vmov.f64 d0, d1 +[^>]*> eeb0 0b41 vmov.f64 d0, d1 +[^>]*> eeb0 0b42 vmov.f64 d0, d2 +[^>]*> eeb0 0b42 vmov.f64 d0, d2 +[^>]*> eeb0 0b44 vmov.f64 d0, d4 +[^>]*> eeb0 0b44 vmov.f64 d0, d4 +[^>]*> eeb0 0b48 vmov.f64 d0, d8 +[^>]*> eeb0 0b48 vmov.f64 d0, d8 +[^>]*> eeb0 0b4f vmov.f64 d0, d15 +[^>]*> eeb0 0b4f vmov.f64 d0, d15 +[^>]*> eeb0 1b40 vmov.f64 d1, d0 +[^>]*> eeb0 1b40 vmov.f64 d1, d0 +[^>]*> eeb0 1b41 vmov.f64 d1, d1 +[^>]*> eeb0 1b41 vmov.f64 d1, d1 +[^>]*> eeb0 1b42 vmov.f64 d1, d2 +[^>]*> eeb0 1b42 vmov.f64 d1, d2 +[^>]*> eeb0 1b44 vmov.f64 d1, d4 +[^>]*> eeb0 1b44 vmov.f64 d1, d4 +[^>]*> eeb0 1b48 vmov.f64 d1, d8 +[^>]*> eeb0 1b48 vmov.f64 d1, d8 +[^>]*> eeb0 1b4f vmov.f64 d1, d15 +[^>]*> eeb0 1b4f vmov.f64 d1, d15 +[^>]*> eeb0 2b40 vmov.f64 d2, d0 +[^>]*> eeb0 2b40 vmov.f64 d2, d0 +[^>]*> eeb0 2b41 vmov.f64 d2, d1 +[^>]*> eeb0 2b41 vmov.f64 d2, d1 +[^>]*> eeb0 2b42 vmov.f64 d2, d2 +[^>]*> eeb0 2b42 vmov.f64 d2, d2 +[^>]*> eeb0 2b44 vmov.f64 d2, d4 +[^>]*> eeb0 2b44 vmov.f64 d2, d4 +[^>]*> eeb0 2b48 vmov.f64 d2, d8 +[^>]*> eeb0 2b48 vmov.f64 d2, d8 +[^>]*> eeb0 2b4f vmov.f64 d2, d15 +[^>]*> eeb0 2b4f vmov.f64 d2, d15 +[^>]*> eeb0 4b40 vmov.f64 d4, d0 +[^>]*> eeb0 4b40 vmov.f64 d4, d0 +[^>]*> eeb0 4b41 vmov.f64 d4, d1 +[^>]*> eeb0 4b41 vmov.f64 d4, d1 +[^>]*> eeb0 4b42 vmov.f64 d4, d2 +[^>]*> eeb0 4b42 vmov.f64 d4, d2 +[^>]*> eeb0 4b44 vmov.f64 d4, d4 +[^>]*> eeb0 4b44 vmov.f64 d4, d4 +[^>]*> eeb0 4b48 vmov.f64 d4, d8 +[^>]*> eeb0 4b48 vmov.f64 d4, d8 +[^>]*> eeb0 4b4f vmov.f64 d4, d15 +[^>]*> eeb0 4b4f vmov.f64 d4, d15 +[^>]*> eeb0 8b40 vmov.f64 d8, d0 +[^>]*> eeb0 8b40 vmov.f64 d8, d0 +[^>]*> eeb0 8b41 vmov.f64 d8, d1 +[^>]*> eeb0 8b41 vmov.f64 d8, d1 +[^>]*> eeb0 8b42 vmov.f64 d8, d2 +[^>]*> eeb0 8b42 vmov.f64 d8, d2 +[^>]*> eeb0 8b44 vmov.f64 d8, d4 +[^>]*> eeb0 8b44 vmov.f64 d8, d4 +[^>]*> eeb0 8b48 vmov.f64 d8, d8 +[^>]*> eeb0 8b48 vmov.f64 d8, d8 +[^>]*> eeb0 8b4f vmov.f64 d8, d15 +[^>]*> eeb0 8b4f vmov.f64 d8, d15 +[^>]*> eeb0 fb40 vmov.f64 d15, d0 +[^>]*> eeb0 fb40 vmov.f64 d15, d0 +[^>]*> eeb0 fb41 vmov.f64 d15, d1 +[^>]*> eeb0 fb41 vmov.f64 d15, d1 +[^>]*> eeb0 fb42 vmov.f64 d15, d2 +[^>]*> eeb0 fb42 vmov.f64 d15, d2 +[^>]*> eeb0 fb44 vmov.f64 d15, d4 +[^>]*> eeb0 fb44 vmov.f64 d15, d4 +[^>]*> eeb0 fb48 vmov.f64 d15, d8 +[^>]*> eeb0 fb48 vmov.f64 d15, d8 +[^>]*> eeb0 fb4f vmov.f64 d15, d15 +[^>]*> eeb0 fb4f vmov.f64 d15, d15 diff --git a/gas/testsuite/gas/arm/mve-vmov-1.s b/gas/testsuite/gas/arm/mve-vmov-1.s index d24fae6..57ca47d 100644 --- a/gas/testsuite/gas/arm/mve-vmov-1.s +++ b/gas/testsuite/gas/arm/mve-vmov-1.s @@ -136,3 +136,10 @@ vmov.i64 q0, #255 @ 0x000000000000000FF vmov \op1, \op2 .endr .endr + +.irp op1, d0, d1, d2, d4, d8, d15 +.irp op2, d0, d1, d2, d4, d8, d15 +vmov \op1, \op2 +vmov.f64 \op1, \op2 +.endr +.endr -- cgit v1.1