From 6655dba246bd164d953fe220a0e3d4eed85bb268 Mon Sep 17 00:00:00 2001 From: Sergey Belyashov Date: Thu, 2 Jan 2020 14:10:40 +0000 Subject: Add support for the GBZ80, Z180, and eZ80 variants of the Z80 architecure. Add an ELF based target for these as well. PR 25224 bfd * Makefile.am: Add z80-elf target support. * configure.ac: Likewise. * targets.c: Likewise. * config.bfd: Add z80-elf target support and new arches: ez80 and z180. * elf32-z80.c: New file. * archures.c: Add new z80 architectures: eZ80 and Z180. * coffcode.h: Likewise. * cpu-z80.c: Likewise. * bfd-in2.h: Likewise plus additional Z80 relocations. * coff-z80.c: Add new relocations for Z80 target and local label check. gas * config/tc-z80.c: Add new architectures: Z180 and eZ80. Add support for assembler code generated by SDCC. Add new relocation types. Add z80-elf target support. * config/tc-z80.h: Add z80-elf target support. Enable dollar local labels. Local labels starts from ".L". * testsuite/gas/all/fwdexp.d: Fix failure due to symbol conflict. * testsuite/gas/all/fwdexp.s: Likewise. * testsuite/gas/z80/suffix.d: Fix failure on ELF target. * testsuite/gas/z80/z80.exp: Add new tests * testsuite/gas/z80/dollar.d: New file. * testsuite/gas/z80/dollar.s: New file. * testsuite/gas/z80/ez80_adl_all.d: New file. * testsuite/gas/z80/ez80_adl_all.s: New file. * testsuite/gas/z80/ez80_adl_suf.d: New file. * testsuite/gas/z80/ez80_isuf.s: New file. * testsuite/gas/z80/ez80_z80_all.d: New file. * testsuite/gas/z80/ez80_z80_all.s: New file. * testsuite/gas/z80/ez80_z80_suf.d: New file. * testsuite/gas/z80/r800_extra.d: New file. * testsuite/gas/z80/r800_extra.s: New file. * testsuite/gas/z80/r800_ii8.d: New file. * testsuite/gas/z80/r800_z80_doc.d: New file. * testsuite/gas/z80/z180.d: New file. * testsuite/gas/z80/z180.s: New file. * testsuite/gas/z80/z180_z80_doc.d: New file. * testsuite/gas/z80/z80_doc.d: New file. * testsuite/gas/z80/z80_doc.s: New file. * testsuite/gas/z80/z80_ii8.d: New file. * testsuite/gas/z80/z80_ii8.s: New file. * testsuite/gas/z80/z80_in_f_c.d: New file. * testsuite/gas/z80/z80_in_f_c.s: New file. * testsuite/gas/z80/z80_op_ii_ld.d: New file. * testsuite/gas/z80/z80_op_ii_ld.s: New file. * testsuite/gas/z80/z80_out_c_0.d: New file. * testsuite/gas/z80/z80_out_c_0.s: New file. * testsuite/gas/z80/z80_reloc.d: New file. * testsuite/gas/z80/z80_reloc.s: New file. * testsuite/gas/z80/z80_sli.d: New file. * testsuite/gas/z80/z80_sli.s: New file. ld * Makefile.am: Add new target z80-elf * configure.tgt: Likewise. * emultempl/z80.em: Add support for eZ80 and Z180 architectures. * emulparams/elf32z80.sh: New file. * emultempl/z80elf.em: Likewise. * testsuite/ld-z80/arch_ez80_adl.d: Likewise. * testsuite/ld-z80/arch_ez80_z80.d: Likewise. * testsuite/ld-z80/arch_r800.d: Likewise. * testsuite/ld-z80/arch_z180.d: Likewise. * testsuite/ld-z80/arch_z80.d: Likewise. * testsuite/ld-z80/comb_arch_ez80_z80.d: Likewise. * testsuite/ld-z80/comb_arch_z180.d: Likewise. * testsuite/ld-z80/labels.s: Likewise. * testsuite/ld-z80/relocs.s: Likewise. * testsuite/ld-z80/relocs_b_ez80.d: Likewise. * testsuite/ld-z80/relocs_b_z80.d: Likewise. * testsuite/ld-z80/relocs_f_z80.d: Likewise. * testsuite/ld-z80/z80.exp: Likewise. opcodes * z80-dis.c: Add support for eZ80 and Z80 instructions. --- gas/doc/as.texi | 47 ++++++++++++++++++++- gas/doc/c-z80.texi | 117 +++++++++++++++++++++++++++++++++++++++-------------- 2 files changed, 131 insertions(+), 33 deletions(-) (limited to 'gas/doc') diff --git a/gas/doc/as.texi b/gas/doc/as.texi index 8957f20..15b33fd 100644 --- a/gas/doc/as.texi +++ b/gas/doc/as.texi @@ -630,7 +630,10 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}. @ifset Z80 @emph{Target Z80 options:} - [@b{-z80}] [@b{-r800}] + [@b{-z80}]|[@b{-z180}]|[@b{-r800}]|[@b{-ez80}]|[@b{-ez80-adl}] + [@b{-strict}]|[@b{-full}] + [@b{-with-inst=@var{INST}[,...]}] [@b{-Wnins @var{INST}[,...]}] + [@b{-without-inst=@var{INST}[,...]}] [@b{-Fins @var{INST}[,...]}] [@b{ -ignore-undocumented-instructions}] [@b{-Wnud}] [@b{ -ignore-unportable-instructions}] [@b{-Wnup}] [@b{ -warn-undocumented-instructions}] [@b{-Wud}] @@ -1943,10 +1946,34 @@ Xtensa processor. The following options are available when @value{AS} is configured for a Z80 family processor. @table @gcctabopt + @item -z80 Assemble for Z80 processor. @item -r800 Assemble for R800 processor. +@item -z180 +Assemble for Z180 processor. +@item -ez80 +Assemble for eZ80 processor in Z80 memory mode by default. +@item -ez80-adl +Assemble for eZ80 processor in ADL memory mode by default. + +@item @code{-colonless} +Accept colonless labels. All names at line begin are treated as labels. +@item @code{-sdcc} +Accept assembler code produces by SDCC. + +@item @code{-strict} +Accept documented instructions only. +@item @code{-full} +Accept all known Z80 instructions. +@item @code{-with-inst=INST[,...]} +@itemx @code{-Wnins INST[,...]} +Enable specified undocumented instruction(s). +@item @code{-without-inst=INST[,...]} +@itemx @code{-Fins INST[,...]} +Disable specified undocumented instruction(s). + @item -ignore-undocumented-instructions @itemx -Wnud Assemble undocumented Z80 instructions that also work on R800 without warning. @@ -1966,6 +1993,22 @@ Treat all undocumented instructions as errors. @itemx -Fup Treat undocumented Z80 instructions that do not work on R800 as errors. @end table + +Folowing undocumented instructions may be enabled/disabled by +@code{-with-inst}/@code{-without-inst}: +@table @gcctabopt +@item @code{idx-reg-halves} +All operations with halves of index registers (IXL, IXH, IYL, IYH). +@item @code{sli} +SLI or SLL instruction. +@item @code{op-ii-ld} +Istructions like @code{ (+),}, where @code{} +is shift or bit manipulation instruction (RLC, SLA, SET, RES...). +@item @code{in-f-c} +Instruction @code{IN F,(C)}. +@item @code{out-c-0} +Instruction @code{OUT (C),0} +@end table @end ifset @c man end @@ -6770,7 +6813,7 @@ If you @code{.set} a global symbol, the value stored in the object file is the last value stored into it. @ifset Z80 -On Z80 @code{set} is a real instruction, use +On Z80 @code{set} is a real instruction, use @code{.set} or @samp{@var{symbol} defl @var{expression}} instead. @end ifset diff --git a/gas/doc/c-z80.texi b/gas/doc/c-z80.texi index b3d3030..a436646 100644 --- a/gas/doc/c-z80.texi +++ b/gas/doc/c-z80.texi @@ -27,41 +27,90 @@ @section Options @cindex Z80 options @cindex options for Z80 -The Zilog Z80 and Ascii R800 version of @code{@value{AS}} have a few machine -dependent options. @table @option @cindex @code{-z80} command-line option, Z80 @item -z80 -Produce code for the Z80 processor. There are additional options to -request warnings and error messages for undocumented instructions. -@item -ignore-undocumented-instructions -@itemx -Wnud +Produce code for the Z80 processor. By default accepted undocumented +operations with halves of index registers (IXL, IXH, IYL, IYH) and +instuction IN F,(C). Other useful undocumented instructions produces +warnings. Undocumented instructions may not work on some CPUs, use +them on your own risk. + +@cindex @code{-r800} command-line option, R800 +@item -r800 +Produce code for the R800 processor. + +@cindex @code{-z180} command-line option, Z180 +@item -z180 +Produce code for the Z180 processor. + +@cindex @code{-ez80} command-line option, eZ80 +@item -ez80 +Produce code for the eZ80 processor in Z80 memory mode by default. + +@cindex @code{-ez80-adl} command-line option, eZ80 +@item -ez80-adl +Produce code for the eZ80 processor in ADL memory mode by default. + +@cindex Compatibility options +@item @code{-colonless} +Accept colonless labels. All names at line begin are treated as labels. + +@item @code{-sdcc} +Accept assembler code produces by SDCC. + +@cindex Undocumented instruction control +@item @code{-strict} +Accept documented instructions only. + +@item @code{-full} +Accept all known Z80 instructions. + +@item @code{-with-inst=INST[,...]} +@itemx @code{-Wnins INST[,...]} +Enable specified undocumented instruction(s). + +@item @code{-without-inst=INST[,...]} +@itemx @code{-Fins INST[,...]} +Disable specified undocumented instruction(s). + +@cindex Obsolete options +@item @code{-ignore-undocumented-instructions} +@itemx @code{-Wnud} Silently assemble undocumented Z80-instructions that have been adopted -as documented R800-instructions. -@item -ignore-unportable-instructions -@itemx -Wnup +as documented R800-instructions . +@item @code{-ignore-unportable-instructions} +@itemx @code{-Wnup} Silently assemble all undocumented Z80-instructions. -@item -warn-undocumented-instructions -@itemx -Wud +@item @code{-warn-undocumented-instructions} +@itemx @code{-Wud} Issue warnings for undocumented Z80-instructions that work on R800, do not assemble other undocumented instructions without warning. -@item -warn-unportable-instructions -@itemx -Wup +@item @code{-warn-unportable-instructions} +@itemx @code{-Wup} Issue warnings for other undocumented Z80-instructions, do not treat any undocumented instructions as errors. -@item -forbid-undocumented-instructions -@itemx -Fud +@item @code{-forbid-undocumented-instructions} +@itemx @code{-Fud} Treat all undocumented z80-instructions as errors. @item -forbid-unportable-instructions -@itemx -Fup +@itemx @code{-Fup} Treat undocumented z80-instructions that do not work on R800 as errors. +@end table -@cindex @code{-r800} command-line option, Z80 -@item -r800 -Produce code for the R800 processor. The assembler does not support -undocumented instructions for the R800. -In line with common practice, @code{@value{AS}} uses Z80 instruction names -for the R800 processor, as far as they exist. +Known undocumented instructions. +@table @option +@cindex Known undocumented instructions +@item @code{idx-reg-halves} +All operations with halves of index registers (IXL, IXH, IYL, IYH). +@item @code{sli} +SLI or SLL instruction. Same as @code{SLA r; INC r}. +@item @code{op-ii-ld} +Istructions like @code{ (+),}. For example: @code{RL (IX+5),C} +@item @code{in-f-c} +Instruction @code{IN F,(C)}. +@item @code{out-c-0} +Instruction @code{OUT (C),0} @end table @cindex Z80 Syntax @@ -158,6 +207,11 @@ compatibility with other assemblers. These are the additional directives in @code{@value{AS}} for the Z80: @table @code +@item assume @var{ADL}@samp{=}@var{expression} +Set ADL status for eZ80. Non-null value enable compilation ADL mode else +used Z80 mode. ADL and Z80 mode produces incompatible object code. Mixing +both of them within one binary may lead problems with disassembler. + @item db @var{expression}|@var{string}[,@var{expression}|@var{string}...] @itemx defb @var{expression}|@var{string}[,@var{expression}|@var{string}...] For each @var{string} the characters are copied to the object file, for @@ -192,9 +246,6 @@ These directives set the value of @var{symbol} to @var{expression}. If @code{equ} is used, it is an error if @var{symbol} is already defined. Symbols defined with @code{equ} are not protected from redefinition. -@item set -This is a normal instruction on Z80, and not an assembler directive. - @item psect @var{name} A synonym for @xref{Section}, no second argument should be given. @ignore @@ -223,18 +274,19 @@ The section is marked as read only. @node Z80 Opcodes @section Opcodes -In line with common practice, Z80 mnemonics are used for both the Z80 and -the R800. +In line with common practice, Z80 mnemonics are used for the Z80, +the Z180, eZ80 and the R800. In many instructions it is possible to use one of the half index registers (@samp{ixl},@samp{ixh},@samp{iyl},@samp{iyh}) in stead of an 8-bit general purpose register. This yields instructions that are -documented on the R800 and undocumented on the Z80. -Similarly @code{in f,(c)} is documented on the R800 and undocumented on -the Z80. +documented on the eZ80 and the R800, undocumented on the Z80 and +unsupported on the Z180. +Similarly @code{in f,(c)} is documented on the R800, undocumented on +the Z80 and unsupported on the Z180 and the eZ80. The assembler also supports the following undocumented Z80-instructions, -that have not been adopted in the R800 instruction set: +that have not been adopted in any other instruction set: @table @code @item out (c),0 Sends zero to the port pointed to by register c. @@ -266,3 +318,6 @@ As above, but with @samp{iy} instead of @samp{ix}. The web site at @uref{http://www.z80.info} is a good starting place to find more information on programming the Z80. +You may enable or disable any of these instructions for any target CPU +even this instruction is not supported by any real CPU of this type. +Useful for custom CPU cores. -- cgit v1.1