From 33eaf5de31b248f84ae108cf0cf4e1664db9ee51 Mon Sep 17 00:00:00 2001 From: Nick Clifton Date: Mon, 23 Jan 2017 15:23:07 +0000 Subject: Fix spelling mistakes and typos in the GAS sources. PR gas/21072 * asintl.h: Fix spelling mistakes and typos. * atof-generic.c: Likewise. * bit_fix.h: Likewise. * config/atof-ieee.c: Likewise. * config/bfin-defs.h: Likewise. * config/bfin-parse.y: Likewise. * config/obj-coff-seh.h: Likewise. * config/obj-coff.c: Likewise. * config/obj-evax.c: Likewise. * config/obj-macho.c: Likewise. * config/rx-parse.y: Likewise. * config/tc-aarch64.c: Likewise. * config/tc-alpha.c: Likewise. * config/tc-arc.c: Likewise. * config/tc-arm.c: Likewise. * config/tc-avr.c: Likewise. * config/tc-bfin.c: Likewise. * config/tc-cr16.c: Likewise. * config/tc-cris.c: Likewise. * config/tc-crx.c: Likewise. * config/tc-d10v.c: Likewise. * config/tc-d30v.c: Likewise. * config/tc-dlx.c: Likewise. * config/tc-epiphany.c: Likewise. * config/tc-frv.c: Likewise. * config/tc-hppa.c: Likewise. * config/tc-i370.c: Likewise. * config/tc-i386-intel.c: Likewise. * config/tc-i386.c: Likewise. * config/tc-i960.c: Likewise. * config/tc-ia64.c: Likewise. * config/tc-m32r.c: Likewise. * config/tc-m68hc11.c: Likewise. * config/tc-m68k.c: Likewise. * config/tc-mcore.c: Likewise. * config/tc-mep.c: Likewise. * config/tc-mep.h: Likewise. * config/tc-metag.c: Likewise. * config/tc-microblaze.c: Likewise. * config/tc-mips.c: Likewise. * config/tc-mmix.c: Likewise. * config/tc-mn10200.c: Likewise. * config/tc-mn10300.c: Likewise. * config/tc-msp430.c: Likewise. * config/tc-msp430.h: Likewise. * config/tc-nds32.c: Likewise. * config/tc-nds32.h: Likewise. * config/tc-nios2.c: Likewise. * config/tc-nios2.h: Likewise. * config/tc-ns32k.c: Likewise. * config/tc-pdp11.c: Likewise. * config/tc-ppc.c: Likewise. * config/tc-pru.c: Likewise. * config/tc-rx.c: Likewise. * config/tc-s390.c: Likewise. * config/tc-score.c: Likewise. * config/tc-score7.c: Likewise. * config/tc-sh.c: Likewise. * config/tc-sh64.c: Likewise. * config/tc-sparc.c: Likewise. * config/tc-tic4x.c: Likewise. * config/tc-tic54x.c: Likewise. * config/tc-v850.c: Likewise. * config/tc-vax.c: Likewise. * config/tc-visium.c: Likewise. * config/tc-xgate.c: Likewise. * config/tc-xtensa.c: Likewise. * config/tc-z80.c: Likewise. * config/tc-z8k.c: Likewise. * config/te-vms.c: Likewise. * config/xtensa-relax.c: Likewise. * doc/as.texinfo: Likewise. * doc/c-arm.texi: Likewise. * doc/c-hppa.texi: Likewise. * doc/c-i370.texi: Likewise. * doc/c-i386.texi: Likewise. * doc/c-m32r.texi: Likewise. * doc/c-m68k.texi: Likewise. * doc/c-mmix.texi: Likewise. * doc/c-msp430.texi: Likewise. * doc/c-nds32.texi: Likewise. * doc/c-ns32k.texi: Likewise. * doc/c-riscv.texi: Likewise. * doc/c-rx.texi: Likewise. * doc/c-s390.texi: Likewise. * doc/c-tic6x.texi: Likewise. * doc/c-tilegx.texi: Likewise. * doc/c-tilepro.texi: Likewise. * doc/c-v850.texi: Likewise. * doc/c-xgate.texi: Likewise. * doc/c-xtensa.texi: Likewise. * dwarf2dbg.c: Likewise. * ecoff.c: Likewise. * itbl-ops.c: Likewise. * listing.c: Likewise. * macro.c: Likewise. * po/gas.pot: Likewise. * read.c: Likewise. * struc-symbol.h: Likewise. * symbols.h: Likewise. * testsuite/gas/arc/relocs-errors.err: Likewise. * write.c: Likewise. --- gas/config/tc-i370.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) (limited to 'gas/config/tc-i370.c') diff --git a/gas/config/tc-i370.c b/gas/config/tc-i370.c index fa6fc75..995aa4c 100644 --- a/gas/config/tc-i370.c +++ b/gas/config/tc-i370.c @@ -276,7 +276,7 @@ register_name (expressionS *expressionP) (void) restore_line_pointer (c); } - /* If numeric, make sure its not out of bounds. */ + /* If numeric, make sure it's not out of bounds. */ if ((0 <= reg_number) && (16 >= reg_number)) { expressionP->X_op = O_register; @@ -443,7 +443,7 @@ md_parse_option (int c, const char *arg) /* Set i370_cpu if it is not already set. Currently defaults to the reasonable superset; - but can be made more fine grained if desred. */ + but can be made more fine grained if desired. */ static void i370_set_cpu (void) @@ -887,7 +887,7 @@ i370_csect (int unused ATTRIBUTE_UNUSED) /* DC Define Const is only partially supported. - For samplecode on what to do, look at i370_elf_cons() above. + For sample code on what to do, look at i370_elf_cons() above. This code handles pseudoops of the style DC D'3.141592653' # in sysv4, .double 3.14159265 DC F'1' # in sysv4, .long 1. */ @@ -1187,7 +1187,7 @@ i370_elf_validate_fix (fixS *fixp, segT seg) start of each pool part. lit_pool_num increments from zero to infinity and uniquely id's - -- its used to generate the *_poolP symbol name. */ + -- it's used to generate the *_poolP symbol name. */ #define MAX_LITERAL_POOL_SIZE 1024 @@ -1325,11 +1325,11 @@ add_to_lit_pool (expressionS *exx, char *name, int sz) /* The symbol setup for the literal pool is done in two steps. First, a symbol that represents the start of the literal pool is created, above, in the add_to_pool() routine. This sym ???_poolP. - However, we don't know what fragment its in until a bit later. + However, we don't know what fragment it's in until a bit later. So we defer the frag_now thing, and the symbol name, until .ltorg time. */ /* Can't use symbol_new here, so have to create a symbol and then at - a later date assign it a value. Thats what these functions do. */ + a later date assign it a value. That's what these functions do. */ static void symbol_locate (symbolS *symbolP, @@ -1549,7 +1549,7 @@ i370_addr_cons (expressionS *exp) =X'AB' one byte =X'abcd' two bytes =X'000000AB' four bytes - =XL4'AB' four bytes, left-padded withn zero. */ + =XL4'AB' four bytes, left-padded with zero. */ if (('X' == name[0]) && (0 > cons_len)) { save = input_line_pointer; @@ -1774,7 +1774,7 @@ i370_drop (int ignore ATTRIBUTE_UNUSED) if (0 == strncmp (now_seg->name, ".text", 5)) { if (iregno != i370_using_text_regno) - as_bad (_("droping register %d in section %s does not match using register %d"), + as_bad (_("dropping register %d in section %s does not match using register %d"), iregno, now_seg->name, i370_using_text_regno); i370_using_text_regno = -1; @@ -1783,11 +1783,11 @@ i370_drop (int ignore ATTRIBUTE_UNUSED) else { if (iregno != i370_using_other_regno) - as_bad (_("droping register %d in section %s does not match using register %d"), + as_bad (_("dropping register %d in section %s does not match using register %d"), iregno, now_seg->name, i370_using_other_regno); if (i370_other_section != now_seg) - as_bad (_("droping register %d in section %s previously used in section %s"), + as_bad (_("dropping register %d in section %s previously used in section %s"), iregno, now_seg->name, i370_other_section->name); i370_using_other_regno = -1; @@ -2009,9 +2009,9 @@ md_assemble (char *str) } /* Perform some off-by-one hacks on the length field of certain instructions. - Its such a shame to have to do this, but the problem is that HLASM got + It's such a shame to have to do this, but the problem is that HLASM got defined so that the lengths differ by one from the actual machine instructions. - this code should probably be moved to a special inster-operand routine. + this code should probably be moved to a special inter-operand routine. Sigh. Affected instructions are Compare Logical, Move and Exclusive OR hack alert -- aren't *all* SS instructions affected ?? */ off_by_one = 0; @@ -2115,7 +2115,7 @@ md_assemble (char *str) input_line_pointer = hold; /* Perform some off-by-one hacks on the length field of certain instructions. - Its such a shame to have to do this, but the problem is that HLASM got + It's such a shame to have to do this, but the problem is that HLASM got defined so that the programmer specifies a length that is one greater than what the machine instruction wants. Sigh. */ if (off_by_one && (0 == strcasecmp ("SS L", operand->name))) @@ -2249,7 +2249,7 @@ md_assemble (char *str) if (size < 1 || size > 4) abort (); - printf (" gwana doo fixup %d \n", i); + printf (" gwana do fixup %d \n", i); fixP = fix_new_exp (frag_now, f - frag_now->fr_literal, size, &fixups[i].exp, reloc_howto->pc_relative, fixups[i].reloc); @@ -2497,7 +2497,7 @@ md_apply_fix (fixS *fixP, valueT * valP, segT seg) We are only prepared to turn a few of the operands into relocs. In fact, we support *zero* operand relocations ... Why? Because we are not expecting the compiler to generate - any operands that need relocation. Due to the 12-bit naturew of + any operands that need relocation. Due to the 12-bit nature of i370 addressing, this would be unusual. */ { const char *sfile; -- cgit v1.1