From b52717c0e104eb603e8189c3c0d3658ef5d903f5 Mon Sep 17 00:00:00 2001 From: Vladimir Radosavljevic Date: Fri, 10 Jun 2016 15:50:13 -0700 Subject: Add support for .MIPS.abiflags and .gnu.attributes sections. elfcpp/ * elfcpp.h (SHT_MIPS_ABIFLAGS): New enum constant. * mips.h (EF_MIPS_FP64, EF_MIPS_NAN2008): New enum constants for processor-specific flags. (E_MIPS_MACH_5900): New enum constant for machine variant. (AFL_REG_NONE, AFL_REG_32, AFL_REG_64, AFL_REG_128): New enum constants. (AFL_ASE_DSP, AFL_ASE_DSPR2, AFL_ASE_EVA, AFL_ASE_MCU, AFL_ASE_MDMX, AFL_ASE_MIPS3D, AFL_ASE_MT, AFL_ASE_SMARTMIPS, AFL_ASE_VIRT, AFL_ASE_MSA, AFL_ASE_MIPS16, AFL_ASE_MICROMIPS, AFL_ASE_XPA): Likewise. (AFL_EXT_XLR, AFL_EXT_OCTEON2, AFL_EXT_OCTEONP, AFL_EXT_LOONGSON_3A, AFL_EXT_OCTEON, AFL_EXT_5900, AFL_EXT_4650, AFL_EXT_4010, AFL_EXT_4100, AFL_EXT_3900, AFL_EXT_10000, AFL_EXT_SB1, AFL_EXT_4111, AFL_EXT_4120, AFL_EXT_5400, AFL_EXT_5500, AFL_EXT_LOONGSON_2E, AFL_EXT_LOONGSON_2F, AFL_EXT_OCTEON3): Likewise. (Tag_GNU_MIPS_ABI_FP, Tag_GNU_MIPS_ABI_MSA): Likewise. (Val_GNU_MIPS_ABI_FP_ANY, Val_GNU_MIPS_ABI_FP_DOUBLE, Val_GNU_MIPS_ABI_FP_SINGLE, Val_GNU_MIPS_ABI_FP_SOFT, Val_GNU_MIPS_ABI_FP_OLD_64,Val_GNU_MIPS_ABI_FP_XX, Val_GNU_MIPS_ABI_FP_64, Val_GNU_MIPS_ABI_FP_64A, Val_GNU_MIPS_ABI_FP_NAN2008, Val_GNU_MIPS_ABI_MSA_ANY, Val_GNU_MIPS_ABI_MSA_128): Likewise. (AFL_FLAGS1_ODDSPREG): New enum constant. gold/ * mips.cc (struct Mips_abiflags): New struct. (Mips_relobj::Mips_relobj): Initialize attributes_section_data_ and abiflags_. (Mips_relobj::~Mips_relobj): Delete object pointed by attributes_section_data_. (Mips_relobj::abiflags): New method. (Mips_relobj::attributes_section_data): Likewise. (Mips_relobj::attributes_section_data_): New data member. (Mips_relobj::abiflags_): Likewise. (class Mips_output_section_abiflags): New class. (Target_mips::Target_mips): Initialize attributes_section_data_, abiflags_ and has_abiflags_section_. (Target_mips::do_should_include_section): Don't emit input .MIPS.abiflags sections to output .MIPS.abiflags. (Target_mips::Mips_mach): Add new enum constants. (Target_mips::mips_isa_ext_mach): New method. (Target_mips::mips_isa_ext): Likewise. (Target_mips::update_abiflags_isa): Likewise. (Target_mips::infer_abiflags): Likewise. (Target_mips::create_abiflags): Likewise. (Target_mips::fp_abi_string): Likewise. (Target_mips::select_fp_abi): Likewise. (Target_mips::merge_obj_attributes): Likewise. (Target_mips::merge_obj_abiflags): Likewise. (Target_mips::level_rev): Likewise. (Target_mips::merge_obj_e_flags): Rename from merge_processor_specific_flags. Remove dyn_obj argument, call update_abiflags_isa when needed, compare NaN encodings and compare FP64 state. (Target_mips::add_machine_extensions): Add two machine extensions and fix one. (Target_mips::attributes_section_data_): New data member. (Target_mips::abiflags_): Likewise. (Target_mips::has_abiflags_section_): Likewise. (Mips_relobj::do_read_symbols): Read .gnu.attributes and .MIPS.abiflags sections if they exists. (Target_mips::elf_mips_mach): Add E_MIPS_MACH_5900 and E_MIPS_MACH_OCTEON3 support. (Target_mips::do_adjust_elf_header): Setup EI_ABIVERSION flag. (Target_mips::do_finalize_sections): Merge .gnu.attributes and .MIPS.abiflags sections from input. Create these sections if needed. (Target_mips::elf_mips_mach_name): Add E_MIPS_MACH_5900 and E_MIPS_MACH_OCTEON3 support, and change strings for E_MIPS_MACH_LS2E, E_MIPS_MACH_LS2F and E_MIPS_MACH_LS3A just to match bfd. --- elfcpp/mips.h | 140 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 140 insertions(+) (limited to 'elfcpp/mips.h') diff --git a/elfcpp/mips.h b/elfcpp/mips.h index 10137ec..a7a9799 100644 --- a/elfcpp/mips.h +++ b/elfcpp/mips.h @@ -193,6 +193,10 @@ enum // Indicates code compiled for a 64-bit machine in 32-bit mode. // (regs are 32-bits wide.) EF_MIPS_32BITMODE = 0x00000100, + // 32-bit machine but FP registers are 64 bit (-mfp64). + EF_MIPS_FP64 = 0x00000200, + /// Code in file uses the IEEE 754-2008 NaN encoding convention. + EF_MIPS_NAN2008 = 0x00000400, // MIPS dynamic EF_MIPS_DYNAMIC = 0x40 }; @@ -220,6 +224,7 @@ enum E_MIPS_MACH_OCTEON2 = 0x008d0000, E_MIPS_MACH_OCTEON3 = 0x008e0000, E_MIPS_MACH_5400 = 0x00910000, + E_MIPS_MACH_5900 = 0x00920000, E_MIPS_MACH_5500 = 0x00980000, E_MIPS_MACH_9000 = 0x00990000, E_MIPS_MACH_LS2E = 0x00A00000, @@ -256,6 +261,141 @@ enum E_MIPS_ARCH_64R6 = 0xa0000000, }; +// Values for the xxx_size bytes of an ABI flags structure. +enum +{ + // No registers. + AFL_REG_NONE = 0x00, + // 32-bit registers. + AFL_REG_32 = 0x01, + // 64-bit registers. + AFL_REG_64 = 0x02, + // 128-bit registers. + AFL_REG_128 = 0x03 +}; + +// Masks for the ases word of an ABI flags structure. +enum +{ + // DSP ASE. + AFL_ASE_DSP = 0x00000001, + // DSP R2 ASE. + AFL_ASE_DSPR2 = 0x00000002, + // Enhanced VA Scheme. + AFL_ASE_EVA = 0x00000004, + // MCU (MicroController) ASE. + AFL_ASE_MCU = 0x00000008, + // MDMX ASE. + AFL_ASE_MDMX = 0x00000010, + // MIPS-3D ASE. + AFL_ASE_MIPS3D = 0x00000020, + // MT ASE. + AFL_ASE_MT = 0x00000040, + // SmartMIPS ASE. + AFL_ASE_SMARTMIPS = 0x00000080, + // VZ ASE. + AFL_ASE_VIRT = 0x00000100, + // MSA ASE. + AFL_ASE_MSA = 0x00000200, + // MIPS16 ASE. + AFL_ASE_MIPS16 = 0x00000400, + // MICROMIPS ASE. + AFL_ASE_MICROMIPS = 0x00000800, + // XPA ASE. + AFL_ASE_XPA = 0x00001000 +}; + +// Values for the isa_ext word of an ABI flags structure. +enum +{ + // RMI Xlr instruction. + AFL_EXT_XLR = 1, + // Cavium Networks Octeon2. + AFL_EXT_OCTEON2 = 2, + // Cavium Networks OcteonP. + AFL_EXT_OCTEONP = 3, + // Loongson 3A. + AFL_EXT_LOONGSON_3A = 4, + // Cavium Networks Octeon. + AFL_EXT_OCTEON = 5, + // MIPS R5900 instruction. + AFL_EXT_5900 = 6, + // MIPS R4650 instruction. + AFL_EXT_4650 = 7, + // LSI R4010 instruction. + AFL_EXT_4010 = 8, + // NEC VR4100 instruction. + AFL_EXT_4100 = 9, + // Toshiba R3900 instruction. + AFL_EXT_3900 = 10, + // MIPS R10000 instruction. + AFL_EXT_10000 = 11, + // Broadcom SB-1 instruction. + AFL_EXT_SB1 = 12, + // NEC VR4111/VR4181 instruction. + AFL_EXT_4111 = 13, + // NEC VR4120 instruction. + AFL_EXT_4120 = 14, + // NEC VR5400 instruction. + AFL_EXT_5400 = 15, + // NEC VR5500 instruction. + AFL_EXT_5500 = 16, + // ST Microelectronics Loongson 2E. + AFL_EXT_LOONGSON_2E = 17, + // ST Microelectronics Loongson 2F. + AFL_EXT_LOONGSON_2F = 18, + // Cavium Networks Octeon3. + AFL_EXT_OCTEON3 = 19 +}; + +// Masks for the flags1 word of an ABI flags structure. +enum +{ + // Uses odd single-precision registers. + AFL_FLAGS1_ODDSPREG = 1 +}; + +// Object attribute tags. +enum +{ + // 0-3 are generic. + // Floating-point ABI used by this object file. + Tag_GNU_MIPS_ABI_FP = 4, + // MSA ABI used by this object file. + Tag_GNU_MIPS_ABI_MSA = 8 +}; + +// Object attribute values. +enum +{ + // Values defined for Tag_GNU_MIPS_ABI_FP. + // Not tagged or not using any ABIs affected by the differences. + Val_GNU_MIPS_ABI_FP_ANY = 0, + // Using hard-float -mdouble-float. + Val_GNU_MIPS_ABI_FP_DOUBLE = 1, + // Using hard-float -msingle-float. + Val_GNU_MIPS_ABI_FP_SINGLE = 2, + // Using soft-float. + Val_GNU_MIPS_ABI_FP_SOFT = 3, + // Using -mips32r2 -mfp64. + Val_GNU_MIPS_ABI_FP_OLD_64 = 4, + // Using -mfpxx + Val_GNU_MIPS_ABI_FP_XX = 5, + // Using -mips32r2 -mfp64. + Val_GNU_MIPS_ABI_FP_64 = 6, + // Using -mips32r2 -mfp64 -mno-odd-spreg. + Val_GNU_MIPS_ABI_FP_64A = 7, + // This is reserved for backward-compatibility with an earlier + // implementation of the MIPS NaN2008 functionality. + Val_GNU_MIPS_ABI_FP_NAN2008 = 8, + + // Values defined for Tag_GNU_MIPS_ABI_MSA. + // Not tagged or not using any ABIs affected by the differences. + Val_GNU_MIPS_ABI_MSA_ANY = 0, + // Using 128-bit MSA. + Val_GNU_MIPS_ABI_MSA_128 = 1 +}; + enum { // Mask to extract ABI version, not really a flag value. -- cgit v1.1