From fb53f5a81a23dd5fc2eac009274e90b9753e1f22 Mon Sep 17 00:00:00 2001 From: Dave Brolley Date: Fri, 28 Oct 2005 19:49:22 +0000 Subject: 2005-10-28 Dave Brolley * All CGEN-generated sources: Regenerate. Contribute the following changes: 2005-09-19 Dave Brolley * disassemble.c (disassemble_init_for_target): Add 'break' to case for bfd_arch_tic4x. Use cgen_bitset_create and cgen_bitset_set for bfd_arch_m32c case. 2005-02-16 Dave Brolley * cgen-dis.in: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename cgen_isa_mask_* to cgen_bitset_*. * cgen-opc.c: Likewise. 2003-11-28 Richard Sandiford * cgen-dis.in (print_insn_@arch@): Fix comparison with cached isas. * *-dis.c: Regenerate. 2003-06-05 DJ Delorie * cgen-dis.in (print_insn_@arch@): Copy prev_isas, don't assign it, as it may point to a reused buffer. Set prev_isas when we change cpus. 2002-12-13 Dave Brolley * cgen-opc.c (cgen_isa_mask_create): New support function for CGEN_ISA_MASK. (cgen_isa_mask_init): Ditto. (cgen_isa_mask_clear): Ditto. (cgen_isa_mask_add): Ditto. (cgen_isa_mask_set): Ditto. (cgen_isa_supported): Ditto. (cgen_isa_mask_compare): Ditto. (cgen_isa_mask_intersection): Ditto. (cgen_isa_mask_copy): Ditto. (cgen_isa_mask_combine): Ditto. * cgen-dis.in (libiberty.h): #include it. (isas): Renamed from 'isa' and now (CGEN_ISA_MASK *). (print_insn_@arch@): Use CGEN_ISA_MASK and support functions. * Makefile.am (CGENDEPS): Add utils-cgen.scm and attrs.scm. * Makefile.in: Regenerated. --- opcodes/ChangeLog | 47 + opcodes/cgen-dis.in | 28 +- opcodes/cgen-opc.c | 148 + opcodes/disassemble.c | 13 +- opcodes/fr30-desc.c | 673 +- opcodes/fr30-desc.h | 44 + opcodes/fr30-dis.c | 28 +- opcodes/fr30-opc.c | 6 +- opcodes/frv-desc.c | 4739 +++++---- opcodes/frv-desc.h | 54 + opcodes/frv-dis.c | 28 +- opcodes/frv-opc.c | 60 +- opcodes/frv-opc.h | 12 +- opcodes/ip2k-desc.c | 521 +- opcodes/ip2k-desc.h | 44 + opcodes/ip2k-dis.c | 28 +- opcodes/ip2k-opc.c | 12 +- opcodes/m32c-asm.c | 4 +- opcodes/m32c-desc.c | 25213 ++++++++++++++++++++++----------------------- opcodes/m32c-desc.h | 46 + opcodes/m32c-dis.c | 28 +- opcodes/m32c-opc.c | 2 +- opcodes/m32r-desc.c | 557 +- opcodes/m32r-desc.h | 50 + opcodes/m32r-dis.c | 28 +- opcodes/m32r-opc.c | 72 +- opcodes/ms1-desc.c | 467 +- opcodes/ms1-desc.h | 52 + opcodes/ms1-dis.c | 28 +- opcodes/openrisc-desc.c | 335 +- opcodes/openrisc-desc.h | 43 + opcodes/openrisc-dis.c | 28 +- opcodes/openrisc-opc.c | 2 +- opcodes/xstormy16-desc.c | 561 +- opcodes/xstormy16-desc.h | 42 + opcodes/xstormy16-dis.c | 28 +- opcodes/xstormy16-opc.c | 10 +- 37 files changed, 17361 insertions(+), 16720 deletions(-) diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index e829630..7e4fd19 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,50 @@ +2005-10-28 Dave Brolley + + * All CGEN-generated sources: Regenerate. + + Contribute the following changes: + 2005-09-19 Dave Brolley + + * disassemble.c (disassemble_init_for_target): Add 'break' to case for + bfd_arch_tic4x. Use cgen_bitset_create and cgen_bitset_set for + bfd_arch_m32c case. + + 2005-02-16 Dave Brolley + + * cgen-dis.in: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename + cgen_isa_mask_* to cgen_bitset_*. + * cgen-opc.c: Likewise. + + 2003-11-28 Richard Sandiford + + * cgen-dis.in (print_insn_@arch@): Fix comparison with cached isas. + * *-dis.c: Regenerate. + + 2003-06-05 DJ Delorie + + * cgen-dis.in (print_insn_@arch@): Copy prev_isas, don't assign + it, as it may point to a reused buffer. Set prev_isas when we + change cpus. + + 2002-12-13 Dave Brolley + + * cgen-opc.c (cgen_isa_mask_create): New support function for + CGEN_ISA_MASK. + (cgen_isa_mask_init): Ditto. + (cgen_isa_mask_clear): Ditto. + (cgen_isa_mask_add): Ditto. + (cgen_isa_mask_set): Ditto. + (cgen_isa_supported): Ditto. + (cgen_isa_mask_compare): Ditto. + (cgen_isa_mask_intersection): Ditto. + (cgen_isa_mask_copy): Ditto. + (cgen_isa_mask_combine): Ditto. + * cgen-dis.in (libiberty.h): #include it. + (isas): Renamed from 'isa' and now (CGEN_ISA_MASK *). + (print_insn_@arch@): Use CGEN_ISA_MASK and support functions. + * Makefile.am (CGENDEPS): Add utils-cgen.scm and attrs.scm. + * Makefile.in: Regenerated. + 2005-10-27 DJ Delorie * m32c-asm.c: Regenerate. diff --git a/opcodes/cgen-dis.in b/opcodes/cgen-dis.in index bc2a7d3..5f29e28 100644 --- a/opcodes/cgen-dis.in +++ b/opcodes/cgen-dis.in @@ -4,7 +4,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. - the resultant file is machine generated, cgen-dis.in isn't - Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005 + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005 Free Software Foundation, Inc. This file is part of the GNU Binutils and GDB, the GNU debugger. @@ -347,7 +347,7 @@ default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) typedef struct cpu_desc_list { struct cpu_desc_list *next; - int isa; + CGEN_BITSET *isa; int mach; int endian; CGEN_CPU_DESC cd; @@ -359,11 +359,12 @@ print_insn_@arch@ (bfd_vma pc, disassemble_info *info) static cpu_desc_list *cd_list = 0; cpu_desc_list *cl = 0; static CGEN_CPU_DESC cd = 0; - static int prev_isa; + static CGEN_BITSET *prev_isa; static int prev_mach; static int prev_endian; int length; - int isa,mach; + CGEN_BITSET *isa; + int mach; int endian = (info->endian == BFD_ENDIAN_BIG ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE); @@ -386,25 +387,34 @@ print_insn_@arch@ (bfd_vma pc, disassemble_info *info) #endif #ifdef CGEN_COMPUTE_ISA - isa = CGEN_COMPUTE_ISA (info); + { + static CGEN_BITSET *permanent_isa; + + if (!permanent_isa) + permanent_isa = cgen_bitset_create (MAX_ISAS); + isa = permanent_isa; + cgen_bitset_clear (isa); + cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info)); + } #else isa = info->insn_sets; #endif /* If we've switched cpu's, try to find a handle we've used before */ if (cd - && (isa != prev_isa + && (cgen_bitset_compare (isa, prev_isa) != 0 || mach != prev_mach || endian != prev_endian)) { cd = 0; for (cl = cd_list; cl; cl = cl->next) { - if (cl->isa == isa && + if (cgen_bitset_compare (cl->isa, isa) == 0 && cl->mach == mach && cl->endian == endian) { cd = cl->cd; + prev_isa = cd->isas; break; } } @@ -420,7 +430,7 @@ print_insn_@arch@ (bfd_vma pc, disassemble_info *info) abort (); mach_name = arch_type->printable_name; - prev_isa = isa; + prev_isa = cgen_bitset_copy (isa); prev_mach = mach; prev_endian = endian; cd = @arch@_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, @@ -433,7 +443,7 @@ print_insn_@arch@ (bfd_vma pc, disassemble_info *info) /* Save this away for future reference. */ cl = xmalloc (sizeof (struct cpu_desc_list)); cl->cd = cd; - cl->isa = isa; + cl->isa = prev_isa; cl->mach = mach; cl->endian = endian; cl->next = cd_list; diff --git a/opcodes/cgen-opc.c b/opcodes/cgen-opc.c index d34aac8..dbc5175 100644 --- a/opcodes/cgen-opc.c +++ b/opcodes/cgen-opc.c @@ -613,3 +613,151 @@ cgen_signed_overflow_ok_p (CGEN_CPU_DESC cd) { return cd->signed_overflow_ok_p; } +/* Functions for manipulating CGEN_BITSET. */ + +/* Create a bit mask. */ +CGEN_BITSET * +cgen_bitset_create (unsigned bit_count) +{ + CGEN_BITSET * mask = xmalloc (sizeof (* mask)); + cgen_bitset_init (mask, bit_count); + return mask; +} + +/* Initialize an existing bit mask. */ + +void +cgen_bitset_init (CGEN_BITSET * mask, unsigned bit_count) +{ + if (! mask) + return; + mask->length = (bit_count / 8) + 1; + mask->bits = xmalloc (mask->length); + cgen_bitset_clear (mask); +} + +/* Clear the bits of a bit mask. */ + +void +cgen_bitset_clear (CGEN_BITSET * mask) +{ + unsigned i; + + if (! mask) + return; + + for (i = 0; i < mask->length; ++i) + mask->bits[i] = 0; +} + +/* Add a bit to a bit mask. */ + +void +cgen_bitset_add (CGEN_BITSET * mask, unsigned bit_num) +{ + int byte_ix, bit_ix; + int bit_mask; + + if (! mask) + return; + byte_ix = bit_num / 8; + bit_ix = bit_num % 8; + bit_mask = 1 << (7 - bit_ix); + mask->bits[byte_ix] |= bit_mask; +} + +/* Set a bit mask. */ + +void +cgen_bitset_set (CGEN_BITSET * mask, unsigned bit_num) +{ + if (! mask) + return; + cgen_bitset_clear (mask); + cgen_bitset_add (mask, bit_num); +} + +/* Test for a bit in a bit mask. + Returns 1 if the bit is found */ + +int +cgen_bitset_contains (CGEN_BITSET * mask, unsigned bit_num) +{ + int byte_ix, bit_ix; + int bit_mask; + + if (! mask) + return 1; /* No bit restrictions. */ + + byte_ix = bit_num / 8; + bit_ix = 7 - (bit_num % 8); + bit_mask = 1 << bit_ix; + return (mask->bits[byte_ix] & bit_mask) >> bit_ix; +} + +/* Compare two bit masks for equality. + Returns 0 if they are equal. */ + +int +cgen_bitset_compare (CGEN_BITSET * mask1, CGEN_BITSET * mask2) +{ + if (mask1 == mask2) + return 0; + if (! mask1 || ! mask2) + return 1; + if (mask1->length != mask2->length) + return 1; + return memcmp (mask1->bits, mask2->bits, mask1->length); +} + +/* Test two bit masks for common bits. + Returns 1 if a common bit is found. */ + +int +cgen_bitset_intersect_p (CGEN_BITSET * mask1, CGEN_BITSET * mask2) +{ + unsigned i, limit; + + if (mask1 == mask2) + return 1; + if (! mask1 || ! mask2) + return 0; + limit = mask1->length < mask2->length ? mask1->length : mask2->length; + + for (i = 0; i < limit; ++i) + if ((mask1->bits[i] & mask2->bits[i])) + return 1; + + return 0; +} + +/* Make a copy of a bit mask. */ + +CGEN_BITSET * +cgen_bitset_copy (CGEN_BITSET * mask) +{ + CGEN_BITSET* newmask; + + if (! mask) + return NULL; + newmask = cgen_bitset_create ((mask->length * 8) - 1); + memcpy (newmask->bits, mask->bits, mask->length); + return newmask; +} + +/* Combine two bit masks. */ + +void +cgen_bitset_union (CGEN_BITSET * mask1, CGEN_BITSET * mask2, + CGEN_BITSET * result) +{ + unsigned i; + + if (! mask1 || ! mask2 || ! result + || mask1->length != mask2->length + || mask1->length != result->length) + return; + + for (i = 0; i < result->length; ++i) + result->bits[i] = mask1->bits[i] | mask2->bits[i]; +} diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c index 5076068..007731a 100644 --- a/opcodes/disassemble.c +++ b/opcodes/disassemble.c @@ -452,14 +452,19 @@ disassemble_init_for_target (struct disassemble_info * info) #ifdef ARCH_tic4x case bfd_arch_tic4x: info->skip_zeroes = 32; + break; #endif #ifdef ARCH_m32c case bfd_arch_m32c: info->endian = BFD_ENDIAN_BIG; - if (info->mach == bfd_mach_m16c) - info->insn_sets = 1 << ISA_M16C; - else - info->insn_sets = 1 << ISA_M32C; + if (! info->insn_sets) + { + info->insn_sets = cgen_bitset_create (ISA_MAX); + if (info->mach == bfd_mach_m16c) + cgen_bitset_set (info->insn_sets, ISA_M16C); + else + cgen_bitset_set (info->insn_sets, ISA_M32C); + } break; #endif default: diff --git a/opcodes/fr30-desc.c b/opcodes/fr30-desc.c index 768fce6..a8c2a35 100644 --- a/opcodes/fr30-desc.c +++ b/opcodes/fr30-desc.c @@ -128,25 +128,25 @@ static const CGEN_MACH fr30_cgen_mach_table[] = { static CGEN_KEYWORD_ENTRY fr30_cgen_opval_gr_names_entries[] = { - { "r0", 0, {0, {0}}, 0, 0 }, - { "r1", 1, {0, {0}}, 0, 0 }, - { "r2", 2, {0, {0}}, 0, 0 }, - { "r3", 3, {0, {0}}, 0, 0 }, - { "r4", 4, {0, {0}}, 0, 0 }, - { "r5", 5, {0, {0}}, 0, 0 }, - { "r6", 6, {0, {0}}, 0, 0 }, - { "r7", 7, {0, {0}}, 0, 0 }, - { "r8", 8, {0, {0}}, 0, 0 }, - { "r9", 9, {0, {0}}, 0, 0 }, - { "r10", 10, {0, {0}}, 0, 0 }, - { "r11", 11, {0, {0}}, 0, 0 }, - { "r12", 12, {0, {0}}, 0, 0 }, - { "r13", 13, {0, {0}}, 0, 0 }, - { "r14", 14, {0, {0}}, 0, 0 }, - { "r15", 15, {0, {0}}, 0, 0 }, - { "ac", 13, {0, {0}}, 0, 0 }, - { "fp", 14, {0, {0}}, 0, 0 }, - { "sp", 15, {0, {0}}, 0, 0 } + { "r0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "r1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "r2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "r3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "r4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "r5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "r6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "r7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "r8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "r9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "r10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "r11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "r12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "r13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "r14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "r15", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "ac", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "fp", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "sp", 15, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD fr30_cgen_opval_gr_names = @@ -158,22 +158,22 @@ CGEN_KEYWORD fr30_cgen_opval_gr_names = static CGEN_KEYWORD_ENTRY fr30_cgen_opval_cr_names_entries[] = { - { "cr0", 0, {0, {0}}, 0, 0 }, - { "cr1", 1, {0, {0}}, 0, 0 }, - { "cr2", 2, {0, {0}}, 0, 0 }, - { "cr3", 3, {0, {0}}, 0, 0 }, - { "cr4", 4, {0, {0}}, 0, 0 }, - { "cr5", 5, {0, {0}}, 0, 0 }, - { "cr6", 6, {0, {0}}, 0, 0 }, - { "cr7", 7, {0, {0}}, 0, 0 }, - { "cr8", 8, {0, {0}}, 0, 0 }, - { "cr9", 9, {0, {0}}, 0, 0 }, - { "cr10", 10, {0, {0}}, 0, 0 }, - { "cr11", 11, {0, {0}}, 0, 0 }, - { "cr12", 12, {0, {0}}, 0, 0 }, - { "cr13", 13, {0, {0}}, 0, 0 }, - { "cr14", 14, {0, {0}}, 0, 0 }, - { "cr15", 15, {0, {0}}, 0, 0 } + { "cr0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "cr1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "cr2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "cr3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "cr4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "cr5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "cr6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "cr7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "cr8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "cr9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "cr10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "cr11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "cr12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "cr13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "cr14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "cr15", 15, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD fr30_cgen_opval_cr_names = @@ -185,12 +185,12 @@ CGEN_KEYWORD fr30_cgen_opval_cr_names = static CGEN_KEYWORD_ENTRY fr30_cgen_opval_dr_names_entries[] = { - { "tbr", 0, {0, {0}}, 0, 0 }, - { "rp", 1, {0, {0}}, 0, 0 }, - { "ssp", 2, {0, {0}}, 0, 0 }, - { "usp", 3, {0, {0}}, 0, 0 }, - { "mdh", 4, {0, {0}}, 0, 0 }, - { "mdl", 5, {0, {0}}, 0, 0 } + { "tbr", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "rp", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "ssp", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "usp", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "mdh", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "mdl", 5, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD fr30_cgen_opval_dr_names = @@ -202,7 +202,7 @@ CGEN_KEYWORD fr30_cgen_opval_dr_names = static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_ps_entries[] = { - { "ps", 0, {0, {0}}, 0, 0 } + { "ps", 0, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD fr30_cgen_opval_h_ps = @@ -214,7 +214,7 @@ CGEN_KEYWORD fr30_cgen_opval_h_ps = static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r13_entries[] = { - { "r13", 0, {0, {0}}, 0, 0 } + { "r13", 0, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD fr30_cgen_opval_h_r13 = @@ -226,7 +226,7 @@ CGEN_KEYWORD fr30_cgen_opval_h_r13 = static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r14_entries[] = { - { "r14", 0, {0, {0}}, 0, 0 } + { "r14", 0, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD fr30_cgen_opval_h_r14 = @@ -238,7 +238,7 @@ CGEN_KEYWORD fr30_cgen_opval_h_r14 = static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r15_entries[] = { - { "r15", 0, {0, {0}}, 0, 0 } + { "r15", 0, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD fr30_cgen_opval_h_r15 = @@ -259,32 +259,32 @@ CGEN_KEYWORD fr30_cgen_opval_h_r15 = const CGEN_HW_ENTRY fr30_cgen_hw_table[] = { - { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<isas; + CGEN_BITSET *isas = cd->isas; unsigned int machs = cd->machs; cd->int_insn_p = CGEN_INT_INSN_P; @@ -1556,7 +1556,7 @@ fr30_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ cd->max_insn_bitsize = 0; for (i = 0; i < MAX_ISAS; ++i) - if (((1 << i) & isas) != 0) + if (cgen_bitset_contains (isas, i)) { const CGEN_ISA *isa = & fr30_cgen_isa_table[i]; @@ -1641,7 +1641,7 @@ fr30_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) { CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); static int init_p; - unsigned int isas = 0; /* 0 = "unspecified" */ + CGEN_BITSET *isas = 0; /* 0 = "unspecified" */ unsigned int machs = 0; /* 0 = "unspecified" */ enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; va_list ap; @@ -1660,7 +1660,7 @@ fr30_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) switch (arg_type) { case CGEN_CPU_OPEN_ISAS : - isas = va_arg (ap, unsigned int); + isas = va_arg (ap, CGEN_BITSET *); break; case CGEN_CPU_OPEN_MACHS : machs = va_arg (ap, unsigned int); @@ -1691,9 +1691,6 @@ fr30_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) machs = (1 << MAX_MACHS) - 1; /* Base mach is always selected. */ machs |= 1; - /* ISA unspecified means "all". */ - if (isas == 0) - isas = (1 << MAX_ISAS) - 1; if (endian == CGEN_ENDIAN_UNKNOWN) { /* ??? If target has only one, could have a default. */ @@ -1701,7 +1698,7 @@ fr30_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) abort (); } - cd->isas = isas; + cd->isas = cgen_bitset_copy (isas); cd->machs = machs; cd->endian = endian; /* FIXME: for the sparc case we can determine insn-endianness statically. diff --git a/opcodes/fr30-desc.h b/opcodes/fr30-desc.h index 7741faf..509a69b 100644 --- a/opcodes/fr30-desc.h +++ b/opcodes/fr30-desc.h @@ -25,6 +25,8 @@ with this program; if not, write to the Free Software Foundation, Inc., #ifndef FR30_CPU_H #define FR30_CPU_H +#include "opcode/cgen-bitset.h" + #define CGEN_ARCH fr30 /* Given symbol S, return fr30_cgen_. */ @@ -156,6 +158,15 @@ typedef enum cgen_ifld_attr { /* Number of non-boolean elements in cgen_ifld_attr. */ #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) +/* cgen_ifld attribute accessor macros. */ +#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0) + /* Enum declaration for fr30 ifield types. */ typedef enum ifield_type { FR30_F_NIL, FR30_F_ANYOF, FR30_F_OP1, FR30_F_OP2 @@ -184,6 +195,13 @@ typedef enum cgen_hw_attr { /* Number of non-boolean elements in cgen_hw_attr. */ #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) +/* cgen_hw attribute accessor macros. */ +#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0) +#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0) +#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0) + /* Enum declaration for fr30 hardware types. */ typedef enum cgen_hw_type { HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR @@ -210,6 +228,18 @@ typedef enum cgen_operand_attr { /* Number of non-boolean elements in cgen_operand_attr. */ #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) +/* cgen_operand attribute accessor macros. */ +#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_HASH_PREFIX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_HASH_PREFIX)) != 0) + /* Enum declaration for fr30 operand types. */ typedef enum cgen_operand_type { FR30_OPERAND_PC, FR30_OPERAND_RI, FR30_OPERAND_RJ, FR30_OPERAND_RIC @@ -246,6 +276,20 @@ typedef enum cgen_insn_attr { /* Number of non-boolean elements in cgen_insn_attr. */ #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) +/* cgen_insn attribute accessor macros. */ +#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0) +#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0) +#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0) +#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0) +#define CGEN_ATTR_CGEN_INSN_NOT_IN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NOT_IN_DELAY_SLOT)) != 0) + /* cgen.h uses things we just defined. */ #include "opcode/cgen.h" diff --git a/opcodes/fr30-dis.c b/opcodes/fr30-dis.c index 0f7c8e8..740e4f4 100644 --- a/opcodes/fr30-dis.c +++ b/opcodes/fr30-dis.c @@ -4,7 +4,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. - the resultant file is machine generated, cgen-dis.in isn't - Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005 + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005 Free Software Foundation, Inc. This file is part of the GNU Binutils and GDB, the GNU debugger. @@ -607,7 +607,7 @@ default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) typedef struct cpu_desc_list { struct cpu_desc_list *next; - int isa; + CGEN_BITSET *isa; int mach; int endian; CGEN_CPU_DESC cd; @@ -619,11 +619,12 @@ print_insn_fr30 (bfd_vma pc, disassemble_info *info) static cpu_desc_list *cd_list = 0; cpu_desc_list *cl = 0; static CGEN_CPU_DESC cd = 0; - static int prev_isa; + static CGEN_BITSET *prev_isa; static int prev_mach; static int prev_endian; int length; - int isa,mach; + CGEN_BITSET *isa; + int mach; int endian = (info->endian == BFD_ENDIAN_BIG ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE); @@ -646,25 +647,34 @@ print_insn_fr30 (bfd_vma pc, disassemble_info *info) #endif #ifdef CGEN_COMPUTE_ISA - isa = CGEN_COMPUTE_ISA (info); + { + static CGEN_BITSET *permanent_isa; + + if (!permanent_isa) + permanent_isa = cgen_bitset_create (MAX_ISAS); + isa = permanent_isa; + cgen_bitset_clear (isa); + cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info)); + } #else isa = info->insn_sets; #endif /* If we've switched cpu's, try to find a handle we've used before */ if (cd - && (isa != prev_isa + && (cgen_bitset_compare (isa, prev_isa) != 0 || mach != prev_mach || endian != prev_endian)) { cd = 0; for (cl = cd_list; cl; cl = cl->next) { - if (cl->isa == isa && + if (cgen_bitset_compare (cl->isa, isa) == 0 && cl->mach == mach && cl->endian == endian) { cd = cl->cd; + prev_isa = cd->isas; break; } } @@ -680,7 +690,7 @@ print_insn_fr30 (bfd_vma pc, disassemble_info *info) abort (); mach_name = arch_type->printable_name; - prev_isa = isa; + prev_isa = cgen_bitset_copy (isa); prev_mach = mach; prev_endian = endian; cd = fr30_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, @@ -693,7 +703,7 @@ print_insn_fr30 (bfd_vma pc, disassemble_info *info) /* Save this away for future reference. */ cl = xmalloc (sizeof (struct cpu_desc_list)); cl->cd = cd; - cl->isa = isa; + cl->isa = prev_isa; cl->mach = mach; cl->endian = endian; cl->next = cd_list; diff --git a/opcodes/fr30-opc.c b/opcodes/fr30-opc.c index 0eefb46..be92c6d 100644 --- a/opcodes/fr30-opc.c +++ b/opcodes/fr30-opc.c @@ -1228,17 +1228,17 @@ static const CGEN_IBASE fr30_cgen_macro_insn_table[] = /* ldi8 $i8,$Ri */ { -1, "ldi8m", "ldi8", 16, - { 0|A(NO_DIS)|A(ALIAS), { (1<isas; + CGEN_BITSET *isas = cd->isas; unsigned int machs = cd->machs; cd->int_insn_p = CGEN_INT_INSN_P; @@ -6269,7 +6269,7 @@ frv_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ cd->max_insn_bitsize = 0; for (i = 0; i < MAX_ISAS; ++i) - if (((1 << i) & isas) != 0) + if (cgen_bitset_contains (isas, i)) { const CGEN_ISA *isa = & frv_cgen_isa_table[i]; @@ -6354,7 +6354,7 @@ frv_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) { CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); static int init_p; - unsigned int isas = 0; /* 0 = "unspecified" */ + CGEN_BITSET *isas = 0; /* 0 = "unspecified" */ unsigned int machs = 0; /* 0 = "unspecified" */ enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; va_list ap; @@ -6373,7 +6373,7 @@ frv_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) switch (arg_type) { case CGEN_CPU_OPEN_ISAS : - isas = va_arg (ap, unsigned int); + isas = va_arg (ap, CGEN_BITSET *); break; case CGEN_CPU_OPEN_MACHS : machs = va_arg (ap, unsigned int); @@ -6404,9 +6404,6 @@ frv_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) machs = (1 << MAX_MACHS) - 1; /* Base mach is always selected. */ machs |= 1; - /* ISA unspecified means "all". */ - if (isas == 0) - isas = (1 << MAX_ISAS) - 1; if (endian == CGEN_ENDIAN_UNKNOWN) { /* ??? If target has only one, could have a default. */ @@ -6414,7 +6411,7 @@ frv_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) abort (); } - cd->isas = isas; + cd->isas = cgen_bitset_copy (isas); cd->machs = machs; cd->endian = endian; /* FIXME: for the sparc case we can determine insn-endianness statically. diff --git a/opcodes/frv-desc.h b/opcodes/frv-desc.h index 8b506dc..d94447f 100644 --- a/opcodes/frv-desc.h +++ b/opcodes/frv-desc.h @@ -25,6 +25,8 @@ with this program; if not, write to the Free Software Foundation, Inc., #ifndef FRV_CPU_H #define FRV_CPU_H +#include "opcode/cgen-bitset.h" + #define CGEN_ARCH frv /* Given symbol S, return frv_cgen_. */ @@ -617,6 +619,15 @@ typedef enum cgen_ifld_attr { /* Number of non-boolean elements in cgen_ifld_attr. */ #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) +/* cgen_ifld attribute accessor macros. */ +#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0) + /* Enum declaration for frv ifield types. */ typedef enum ifield_type { FRV_F_NIL, FRV_F_ANYOF, FRV_F_PACK, FRV_F_OP @@ -661,6 +672,13 @@ typedef enum cgen_hw_attr { /* Number of non-boolean elements in cgen_hw_attr. */ #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) +/* cgen_hw attribute accessor macros. */ +#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0) +#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0) +#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0) + /* Enum declaration for frv hardware types. */ typedef enum cgen_hw_type { HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR @@ -693,6 +711,18 @@ typedef enum cgen_operand_attr { /* Number of non-boolean elements in cgen_operand_attr. */ #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) +/* cgen_operand attribute accessor macros. */ +#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_HASH_PREFIX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_HASH_PREFIX)) != 0) + /* Enum declaration for frv operand types. */ typedef enum cgen_operand_type { FRV_OPERAND_PC, FRV_OPERAND_PACK, FRV_OPERAND_GRI, FRV_OPERAND_GRJ @@ -742,6 +772,30 @@ typedef enum cgen_insn_attr { /* Number of non-boolean elements in cgen_insn_attr. */ #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) +/* cgen_insn attribute accessor macros. */ +#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_UNIT_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_UNIT-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_FR400_MAJOR_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_FR400_MAJOR-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_FR450_MAJOR_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_FR450_MAJOR-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_FR500_MAJOR_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_FR500_MAJOR-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_FR550_MAJOR_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_FR550_MAJOR-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0) +#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0) +#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0) +#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0) +#define CGEN_ATTR_CGEN_INSN_PRIVILEGED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PRIVILEGED)) != 0) +#define CGEN_ATTR_CGEN_INSN_NON_EXCEPTING_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NON_EXCEPTING)) != 0) +#define CGEN_ATTR_CGEN_INSN_CONDITIONAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_CONDITIONAL)) != 0) +#define CGEN_ATTR_CGEN_INSN_FR_ACCESS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_FR_ACCESS)) != 0) +#define CGEN_ATTR_CGEN_INSN_PRESERVE_OVF_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PRESERVE_OVF)) != 0) +#define CGEN_ATTR_CGEN_INSN_AUDIO_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_AUDIO)) != 0) + /* cgen.h uses things we just defined. */ #include "opcode/cgen.h" diff --git a/opcodes/frv-dis.c b/opcodes/frv-dis.c index a82fe2b..f74eb62 100644 --- a/opcodes/frv-dis.c +++ b/opcodes/frv-dis.c @@ -4,7 +4,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. - the resultant file is machine generated, cgen-dis.in isn't - Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005 + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005 Free Software Foundation, Inc. This file is part of the GNU Binutils and GDB, the GNU debugger. @@ -704,7 +704,7 @@ default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) typedef struct cpu_desc_list { struct cpu_desc_list *next; - int isa; + CGEN_BITSET *isa; int mach; int endian; CGEN_CPU_DESC cd; @@ -716,11 +716,12 @@ print_insn_frv (bfd_vma pc, disassemble_info *info) static cpu_desc_list *cd_list = 0; cpu_desc_list *cl = 0; static CGEN_CPU_DESC cd = 0; - static int prev_isa; + static CGEN_BITSET *prev_isa; static int prev_mach; static int prev_endian; int length; - int isa,mach; + CGEN_BITSET *isa; + int mach; int endian = (info->endian == BFD_ENDIAN_BIG ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE); @@ -743,25 +744,34 @@ print_insn_frv (bfd_vma pc, disassemble_info *info) #endif #ifdef CGEN_COMPUTE_ISA - isa = CGEN_COMPUTE_ISA (info); + { + static CGEN_BITSET *permanent_isa; + + if (!permanent_isa) + permanent_isa = cgen_bitset_create (MAX_ISAS); + isa = permanent_isa; + cgen_bitset_clear (isa); + cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info)); + } #else isa = info->insn_sets; #endif /* If we've switched cpu's, try to find a handle we've used before */ if (cd - && (isa != prev_isa + && (cgen_bitset_compare (isa, prev_isa) != 0 || mach != prev_mach || endian != prev_endian)) { cd = 0; for (cl = cd_list; cl; cl = cl->next) { - if (cl->isa == isa && + if (cgen_bitset_compare (cl->isa, isa) == 0 && cl->mach == mach && cl->endian == endian) { cd = cl->cd; + prev_isa = cd->isas; break; } } @@ -777,7 +787,7 @@ print_insn_frv (bfd_vma pc, disassemble_info *info) abort (); mach_name = arch_type->printable_name; - prev_isa = isa; + prev_isa = cgen_bitset_copy (isa); prev_mach = mach; prev_endian = endian; cd = frv_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, @@ -790,7 +800,7 @@ print_insn_frv (bfd_vma pc, disassemble_info *info) /* Save this away for future reference. */ cl = xmalloc (sizeof (struct cpu_desc_list)); cl->cd = cd; - cl->isa = isa; + cl->isa = prev_isa; cl->mach = mach; cl->endian = endian; cl->next = cd_list; diff --git a/opcodes/frv-opc.c b/opcodes/frv-opc.c index 293ae61..d3e2b35 100644 --- a/opcodes/frv-opc.c +++ b/opcodes/frv-opc.c @@ -38,7 +38,7 @@ with this program; if not, write to the Free Software Foundation, Inc., development tree. */ bfd_boolean -frv_is_branch_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach) +frv_is_branch_major (CGEN_ATTR_VALUE_ENUM_TYPE major, unsigned long mach) { switch (mach) { @@ -62,7 +62,7 @@ frv_is_branch_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach) /* Returns TRUE if {MAJOR,MACH} supports floating point insns. */ bfd_boolean -frv_is_float_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach) +frv_is_float_major (CGEN_ATTR_VALUE_ENUM_TYPE major, unsigned long mach) { switch (mach) { @@ -81,7 +81,7 @@ frv_is_float_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach) /* Returns TRUE if {MAJOR,MACH} supports media insns. */ bfd_boolean -frv_is_media_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach) +frv_is_media_major (CGEN_ATTR_VALUE_ENUM_TYPE major, unsigned long mach) { switch (mach) { @@ -225,7 +225,7 @@ static VLIW_COMBO fr550_allowed_vliw[] = /* Some insns are assigned specialized implementation units which map to different actual implementation units on different machines. These tables perform that mapping. */ -static CGEN_ATTR_VALUE_TYPE fr400_unit_mapping[] = +static CGEN_ATTR_VALUE_ENUM_TYPE fr400_unit_mapping[] = { /* unit in insn actual unit */ /* NIL */ UNIT_NIL, @@ -260,7 +260,7 @@ static CGEN_ATTR_VALUE_TYPE fr400_unit_mapping[] = /* Some insns are assigned specialized implementation units which map to different actual implementation units on different machines. These tables perform that mapping. */ -static CGEN_ATTR_VALUE_TYPE fr450_unit_mapping[] = +static CGEN_ATTR_VALUE_ENUM_TYPE fr450_unit_mapping[] = { /* unit in insn actual unit */ /* NIL */ UNIT_NIL, @@ -292,7 +292,7 @@ static CGEN_ATTR_VALUE_TYPE fr450_unit_mapping[] = /* MCLRACC-1*/ UNIT_FM0 /* mclracc,A==1 insn only in FM0 unit. */ }; -static CGEN_ATTR_VALUE_TYPE fr500_unit_mapping[] = +static CGEN_ATTR_VALUE_ENUM_TYPE fr500_unit_mapping[] = { /* unit in insn actual unit */ /* NIL */ UNIT_NIL, @@ -324,7 +324,7 @@ static CGEN_ATTR_VALUE_TYPE fr500_unit_mapping[] = /* MCLRACC-1*/ UNIT_FM01 /* mclracc,A==1 in FM0 or FM1 unit. */ }; -static CGEN_ATTR_VALUE_TYPE fr550_unit_mapping[] = +static CGEN_ATTR_VALUE_ENUM_TYPE fr550_unit_mapping[] = { /* unit in insn actual unit */ /* NIL */ UNIT_NIL, @@ -390,7 +390,7 @@ frv_vliw_reset (FRV_VLIW *vliw, unsigned long mach, unsigned long elf_flags) *_allowed_vliw tables above. */ static bfd_boolean match_unit (FRV_VLIW *vliw, - CGEN_ATTR_VALUE_TYPE unit1, CGEN_ATTR_VALUE_TYPE unit2) + CGEN_ATTR_VALUE_ENUM_TYPE unit1, CGEN_ATTR_VALUE_ENUM_TYPE unit2) { /* Map any specialized implementation units to actual ones. */ unit1 = vliw->unit_mapping[unit1]; @@ -442,7 +442,7 @@ match_vliw (VLIW_COMBO *vliw1, VLIW_COMBO *vliw2, int vliw_size) If one is found then return it. Otherwise return NULL. */ static VLIW_COMBO * -add_next_to_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE unit) +add_next_to_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE unit) { int next = vliw->next_slot; VLIW_COMBO *current = vliw->current_vliw; @@ -473,7 +473,7 @@ add_next_to_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE unit) Returns TRUE if found, FALSE otherwise. */ static bfd_boolean -find_major_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major) +find_major_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE major) { int i; @@ -488,7 +488,7 @@ find_major_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major) types. */ static bfd_boolean -fr400_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major) +fr400_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE major) { /* In the cpu file, all media insns are represented as being allowed in both media units. This makes it easier since this is the case for fr500. @@ -508,9 +508,9 @@ fr400_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major) } static bfd_boolean -fr450_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major) +fr450_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE major) { - CGEN_ATTR_VALUE_TYPE other_major; + CGEN_ATTR_VALUE_ENUM_TYPE other_major; /* Our caller guarantees there's at least one other instruction. */ other_major = CGEN_INSN_ATTR_VALUE (vliw->insn[0], CGEN_INSN_FR450_MAJOR); @@ -543,7 +543,7 @@ fr450_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major) } static bfd_boolean -find_unit_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE unit) +find_unit_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE unit) { int i; @@ -556,8 +556,8 @@ find_unit_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE unit) static bfd_boolean find_major_in_slot (FRV_VLIW *vliw, - CGEN_ATTR_VALUE_TYPE major, - CGEN_ATTR_VALUE_TYPE slot) + CGEN_ATTR_VALUE_ENUM_TYPE major, + CGEN_ATTR_VALUE_ENUM_TYPE slot) { int i; @@ -612,11 +612,11 @@ fr550_find_float_in_vliw (FRV_VLIW *vliw) static bfd_boolean fr550_check_insn_major_constraints (FRV_VLIW *vliw, - CGEN_ATTR_VALUE_TYPE major, + CGEN_ATTR_VALUE_ENUM_TYPE major, const CGEN_INSN *insn) { - CGEN_ATTR_VALUE_TYPE unit; - CGEN_ATTR_VALUE_TYPE slot = (*vliw->current_vliw)[vliw->next_slot]; + CGEN_ATTR_VALUE_ENUM_TYPE unit; + CGEN_ATTR_VALUE_ENUM_TYPE slot = (*vliw->current_vliw)[vliw->next_slot]; switch (slot) { case UNIT_I2: @@ -662,7 +662,7 @@ fr550_check_insn_major_constraints (FRV_VLIW *vliw, } static bfd_boolean -fr500_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major) +fr500_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE major) { /* TODO: A table might be faster for some of the more complex instances here. */ @@ -770,7 +770,7 @@ fr500_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major) static bfd_boolean check_insn_major_constraints (FRV_VLIW *vliw, - CGEN_ATTR_VALUE_TYPE major, + CGEN_ATTR_VALUE_ENUM_TYPE major, const CGEN_INSN *insn) { switch (vliw->mach) @@ -796,8 +796,8 @@ int frv_vliw_add_insn (FRV_VLIW *vliw, const CGEN_INSN *insn) { int index; - CGEN_ATTR_VALUE_TYPE major; - CGEN_ATTR_VALUE_TYPE unit; + CGEN_ATTR_VALUE_ENUM_TYPE major; + CGEN_ATTR_VALUE_ENUM_TYPE unit; VLIW_COMBO *new_vliw; if (vliw->constraint_violation || CGEN_INSN_INVALID_P (insn)) @@ -6046,37 +6046,37 @@ static const CGEN_IBASE frv_cgen_macro_insn_table[] = /* nop$pack */ { -1, "nop", "nop", 32, - { 0|A(ALIAS), { (1<isas; + CGEN_BITSET *isas = cd->isas; unsigned int machs = cd->machs; cd->int_insn_p = CGEN_INT_INSN_P; @@ -985,7 +985,7 @@ ip2k_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ cd->max_insn_bitsize = 0; for (i = 0; i < MAX_ISAS; ++i) - if (((1 << i) & isas) != 0) + if (cgen_bitset_contains (isas, i)) { const CGEN_ISA *isa = & ip2k_cgen_isa_table[i]; @@ -1070,7 +1070,7 @@ ip2k_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) { CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); static int init_p; - unsigned int isas = 0; /* 0 = "unspecified" */ + CGEN_BITSET *isas = 0; /* 0 = "unspecified" */ unsigned int machs = 0; /* 0 = "unspecified" */ enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; va_list ap; @@ -1089,7 +1089,7 @@ ip2k_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) switch (arg_type) { case CGEN_CPU_OPEN_ISAS : - isas = va_arg (ap, unsigned int); + isas = va_arg (ap, CGEN_BITSET *); break; case CGEN_CPU_OPEN_MACHS : machs = va_arg (ap, unsigned int); @@ -1120,9 +1120,6 @@ ip2k_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) machs = (1 << MAX_MACHS) - 1; /* Base mach is always selected. */ machs |= 1; - /* ISA unspecified means "all". */ - if (isas == 0) - isas = (1 << MAX_ISAS) - 1; if (endian == CGEN_ENDIAN_UNKNOWN) { /* ??? If target has only one, could have a default. */ @@ -1130,7 +1127,7 @@ ip2k_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) abort (); } - cd->isas = isas; + cd->isas = cgen_bitset_copy (isas); cd->machs = machs; cd->endian = endian; /* FIXME: for the sparc case we can determine insn-endianness statically. diff --git a/opcodes/ip2k-desc.h b/opcodes/ip2k-desc.h index fa85fbd..125849f 100644 --- a/opcodes/ip2k-desc.h +++ b/opcodes/ip2k-desc.h @@ -25,6 +25,8 @@ with this program; if not, write to the Free Software Foundation, Inc., #ifndef IP2K_CPU_H #define IP2K_CPU_H +#include "opcode/cgen-bitset.h" + #define CGEN_ARCH ip2k /* Given symbol S, return ip2k_cgen_. */ @@ -160,6 +162,15 @@ typedef enum cgen_ifld_attr { /* Number of non-boolean elements in cgen_ifld_attr. */ #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) +/* cgen_ifld attribute accessor macros. */ +#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0) + /* Enum declaration for ip2k ifield types. */ typedef enum ifield_type { IP2K_F_NIL, IP2K_F_ANYOF, IP2K_F_IMM8, IP2K_F_REG @@ -182,6 +193,13 @@ typedef enum cgen_hw_attr { /* Number of non-boolean elements in cgen_hw_attr. */ #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) +/* cgen_hw attribute accessor macros. */ +#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0) +#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0) +#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0) + /* Enum declaration for ip2k hardware types. */ typedef enum cgen_hw_type { HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR @@ -204,6 +222,17 @@ typedef enum cgen_operand_attr { /* Number of non-boolean elements in cgen_operand_attr. */ #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) +/* cgen_operand attribute accessor macros. */ +#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) + /* Enum declaration for ip2k operand types. */ typedef enum cgen_operand_type { IP2K_OPERAND_PC, IP2K_OPERAND_ADDR16CJP, IP2K_OPERAND_FR, IP2K_OPERAND_LIT8 @@ -231,6 +260,21 @@ typedef enum cgen_insn_attr { /* Number of non-boolean elements in cgen_insn_attr. */ #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) +/* cgen_insn attribute accessor macros. */ +#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0) +#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0) +#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0) +#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0) +#define CGEN_ATTR_CGEN_INSN_EXT_SKIP_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_EXT_SKIP_INSN)) != 0) +#define CGEN_ATTR_CGEN_INSN_SKIPA_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIPA)) != 0) + /* cgen.h uses things we just defined. */ #include "opcode/cgen.h" diff --git a/opcodes/ip2k-dis.c b/opcodes/ip2k-dis.c index 95cb9e4..b80e97f 100644 --- a/opcodes/ip2k-dis.c +++ b/opcodes/ip2k-dis.c @@ -4,7 +4,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. - the resultant file is machine generated, cgen-dis.in isn't - Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005 + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005 Free Software Foundation, Inc. This file is part of the GNU Binutils and GDB, the GNU debugger. @@ -596,7 +596,7 @@ default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) typedef struct cpu_desc_list { struct cpu_desc_list *next; - int isa; + CGEN_BITSET *isa; int mach; int endian; CGEN_CPU_DESC cd; @@ -608,11 +608,12 @@ print_insn_ip2k (bfd_vma pc, disassemble_info *info) static cpu_desc_list *cd_list = 0; cpu_desc_list *cl = 0; static CGEN_CPU_DESC cd = 0; - static int prev_isa; + static CGEN_BITSET *prev_isa; static int prev_mach; static int prev_endian; int length; - int isa,mach; + CGEN_BITSET *isa; + int mach; int endian = (info->endian == BFD_ENDIAN_BIG ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE); @@ -635,25 +636,34 @@ print_insn_ip2k (bfd_vma pc, disassemble_info *info) #endif #ifdef CGEN_COMPUTE_ISA - isa = CGEN_COMPUTE_ISA (info); + { + static CGEN_BITSET *permanent_isa; + + if (!permanent_isa) + permanent_isa = cgen_bitset_create (MAX_ISAS); + isa = permanent_isa; + cgen_bitset_clear (isa); + cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info)); + } #else isa = info->insn_sets; #endif /* If we've switched cpu's, try to find a handle we've used before */ if (cd - && (isa != prev_isa + && (cgen_bitset_compare (isa, prev_isa) != 0 || mach != prev_mach || endian != prev_endian)) { cd = 0; for (cl = cd_list; cl; cl = cl->next) { - if (cl->isa == isa && + if (cgen_bitset_compare (cl->isa, isa) == 0 && cl->mach == mach && cl->endian == endian) { cd = cl->cd; + prev_isa = cd->isas; break; } } @@ -669,7 +679,7 @@ print_insn_ip2k (bfd_vma pc, disassemble_info *info) abort (); mach_name = arch_type->printable_name; - prev_isa = isa; + prev_isa = cgen_bitset_copy (isa); prev_mach = mach; prev_endian = endian; cd = ip2k_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, @@ -682,7 +692,7 @@ print_insn_ip2k (bfd_vma pc, disassemble_info *info) /* Save this away for future reference. */ cl = xmalloc (sizeof (struct cpu_desc_list)); cl->cd = cd; - cl->isa = isa; + cl->isa = prev_isa; cl->mach = mach; cl->endian = endian; cl->next = cd_list; diff --git a/opcodes/ip2k-opc.c b/opcodes/ip2k-opc.c index dd4648f..30a734e 100644 --- a/opcodes/ip2k-opc.c +++ b/opcodes/ip2k-opc.c @@ -726,32 +726,32 @@ static const CGEN_IBASE ip2k_cgen_macro_insn_table[] = /* sc */ { -1, "sc", "sc", 16, - { 0|A(ALIAS), { (1<machs) - && (isas & cd->isas)); + && cgen_bitset_intersect_p (& isas, cd->isas)); } /* Parse a set of registers, R0,R1,A0,A1,SB,FB. */ diff --git a/opcodes/m32c-desc.c b/opcodes/m32c-desc.c index f0b56ee..12b9a1b 100644 --- a/opcodes/m32c-desc.c +++ b/opcodes/m32c-desc.c @@ -134,10 +134,10 @@ static const CGEN_MACH m32c_cgen_mach_table[] = { static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_entries[] = { - { "r0", 0, {0, {0}}, 0, 0 }, - { "r1", 1, {0, {0}}, 0, 0 }, - { "r2", 2, {0, {0}}, 0, 0 }, - { "r3", 3, {0, {0}}, 0, 0 } + { "r0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "r1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "r2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "r3", 3, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_gr = @@ -149,10 +149,10 @@ CGEN_KEYWORD m32c_cgen_opval_h_gr = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_QI_entries[] = { - { "r0l", 0, {0, {0}}, 0, 0 }, - { "r0h", 1, {0, {0}}, 0, 0 }, - { "r1l", 2, {0, {0}}, 0, 0 }, - { "r1h", 3, {0, {0}}, 0, 0 } + { "r0l", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "r0h", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "r1l", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "r1h", 3, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_gr_QI = @@ -164,10 +164,10 @@ CGEN_KEYWORD m32c_cgen_opval_h_gr_QI = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_HI_entries[] = { - { "r0", 0, {0, {0}}, 0, 0 }, - { "r1", 1, {0, {0}}, 0, 0 }, - { "r2", 2, {0, {0}}, 0, 0 }, - { "r3", 3, {0, {0}}, 0, 0 } + { "r0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "r1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "r2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "r3", 3, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_gr_HI = @@ -179,8 +179,8 @@ CGEN_KEYWORD m32c_cgen_opval_h_gr_HI = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_SI_entries[] = { - { "r2r0", 0, {0, {0}}, 0, 0 }, - { "r3r1", 1, {0, {0}}, 0, 0 } + { "r2r0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "r3r1", 1, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_gr_SI = @@ -192,8 +192,8 @@ CGEN_KEYWORD m32c_cgen_opval_h_gr_SI = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_ext_QI_entries[] = { - { "r0l", 0, {0, {0}}, 0, 0 }, - { "r1l", 1, {0, {0}}, 0, 0 } + { "r0l", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "r1l", 1, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_gr_ext_QI = @@ -205,8 +205,8 @@ CGEN_KEYWORD m32c_cgen_opval_h_gr_ext_QI = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_ext_HI_entries[] = { - { "r0", 0, {0, {0}}, 0, 0 }, - { "r1", 1, {0, {0}}, 0, 0 } + { "r0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "r1", 1, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_gr_ext_HI = @@ -218,7 +218,7 @@ CGEN_KEYWORD m32c_cgen_opval_h_gr_ext_HI = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0l_entries[] = { - { "r0l", 0, {0, {0}}, 0, 0 } + { "r0l", 0, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_r0l = @@ -230,7 +230,7 @@ CGEN_KEYWORD m32c_cgen_opval_h_r0l = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0h_entries[] = { - { "r0h", 0, {0, {0}}, 0, 0 } + { "r0h", 0, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_r0h = @@ -242,7 +242,7 @@ CGEN_KEYWORD m32c_cgen_opval_h_r0h = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1l_entries[] = { - { "r1l", 0, {0, {0}}, 0, 0 } + { "r1l", 0, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_r1l = @@ -254,7 +254,7 @@ CGEN_KEYWORD m32c_cgen_opval_h_r1l = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1h_entries[] = { - { "r1h", 0, {0, {0}}, 0, 0 } + { "r1h", 0, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_r1h = @@ -266,7 +266,7 @@ CGEN_KEYWORD m32c_cgen_opval_h_r1h = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0_entries[] = { - { "r0", 0, {0, {0}}, 0, 0 } + { "r0", 0, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_r0 = @@ -278,7 +278,7 @@ CGEN_KEYWORD m32c_cgen_opval_h_r0 = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1_entries[] = { - { "r1", 0, {0, {0}}, 0, 0 } + { "r1", 0, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_r1 = @@ -290,7 +290,7 @@ CGEN_KEYWORD m32c_cgen_opval_h_r1 = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r2_entries[] = { - { "r2", 0, {0, {0}}, 0, 0 } + { "r2", 0, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_r2 = @@ -302,7 +302,7 @@ CGEN_KEYWORD m32c_cgen_opval_h_r2 = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r3_entries[] = { - { "r3", 0, {0, {0}}, 0, 0 } + { "r3", 0, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_r3 = @@ -314,8 +314,8 @@ CGEN_KEYWORD m32c_cgen_opval_h_r3 = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0l_r0h_entries[] = { - { "r0l", 0, {0, {0}}, 0, 0 }, - { "r0h", 1, {0, {0}}, 0, 0 } + { "r0l", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "r0h", 1, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_r0l_r0h = @@ -327,7 +327,7 @@ CGEN_KEYWORD m32c_cgen_opval_h_r0l_r0h = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r2r0_entries[] = { - { "r2r0", 0, {0, {0}}, 0, 0 } + { "r2r0", 0, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_r2r0 = @@ -339,7 +339,7 @@ CGEN_KEYWORD m32c_cgen_opval_h_r2r0 = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r3r1_entries[] = { - { "r3r1", 0, {0, {0}}, 0, 0 } + { "r3r1", 0, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_r3r1 = @@ -351,7 +351,7 @@ CGEN_KEYWORD m32c_cgen_opval_h_r3r1 = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1r2r0_entries[] = { - { "r1r2r0", 0, {0, {0}}, 0, 0 } + { "r1r2r0", 0, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_r1r2r0 = @@ -363,8 +363,8 @@ CGEN_KEYWORD m32c_cgen_opval_h_r1r2r0 = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_entries[] = { - { "a0", 0, {0, {0}}, 0, 0 }, - { "a1", 1, {0, {0}}, 0, 0 } + { "a0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "a1", 1, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_ar = @@ -376,8 +376,8 @@ CGEN_KEYWORD m32c_cgen_opval_h_ar = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_QI_entries[] = { - { "a0", 0, {0, {0}}, 0, 0 }, - { "a1", 1, {0, {0}}, 0, 0 } + { "a0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "a1", 1, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_ar_QI = @@ -389,8 +389,8 @@ CGEN_KEYWORD m32c_cgen_opval_h_ar_QI = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_HI_entries[] = { - { "a0", 0, {0, {0}}, 0, 0 }, - { "a1", 1, {0, {0}}, 0, 0 } + { "a0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "a1", 1, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_ar_HI = @@ -402,7 +402,7 @@ CGEN_KEYWORD m32c_cgen_opval_h_ar_HI = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_SI_entries[] = { - { "a1a0", 0, {0, {0}}, 0, 0 } + { "a1a0", 0, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_ar_SI = @@ -414,7 +414,7 @@ CGEN_KEYWORD m32c_cgen_opval_h_ar_SI = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_a0_entries[] = { - { "a0", 0, {0, {0}}, 0, 0 } + { "a0", 0, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_a0 = @@ -426,7 +426,7 @@ CGEN_KEYWORD m32c_cgen_opval_h_a0 = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_a1_entries[] = { - { "a1", 1, {0, {0}}, 0, 0 } + { "a1", 1, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_a1 = @@ -438,24 +438,24 @@ CGEN_KEYWORD m32c_cgen_opval_h_a1 = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16_entries[] = { - { "geu", 0, {0, {0}}, 0, 0 }, - { "c", 0, {0, {0}}, 0, 0 }, - { "gtu", 1, {0, {0}}, 0, 0 }, - { "eq", 2, {0, {0}}, 0, 0 }, - { "z", 2, {0, {0}}, 0, 0 }, - { "n", 3, {0, {0}}, 0, 0 }, - { "le", 4, {0, {0}}, 0, 0 }, - { "o", 5, {0, {0}}, 0, 0 }, - { "ge", 6, {0, {0}}, 0, 0 }, - { "ltu", 248, {0, {0}}, 0, 0 }, - { "nc", 248, {0, {0}}, 0, 0 }, - { "leu", 249, {0, {0}}, 0, 0 }, - { "ne", 250, {0, {0}}, 0, 0 }, - { "nz", 250, {0, {0}}, 0, 0 }, - { "pz", 251, {0, {0}}, 0, 0 }, - { "gt", 252, {0, {0}}, 0, 0 }, - { "no", 253, {0, {0}}, 0, 0 }, - { "lt", 254, {0, {0}}, 0, 0 } + { "geu", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "c", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "gtu", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "eq", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "z", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "n", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "le", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "o", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "ge", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "ltu", 248, {0, {{{0, 0}}}}, 0, 0 }, + { "nc", 248, {0, {{{0, 0}}}}, 0, 0 }, + { "leu", 249, {0, {{{0, 0}}}}, 0, 0 }, + { "ne", 250, {0, {{{0, 0}}}}, 0, 0 }, + { "nz", 250, {0, {{{0, 0}}}}, 0, 0 }, + { "pz", 251, {0, {{{0, 0}}}}, 0, 0 }, + { "gt", 252, {0, {{{0, 0}}}}, 0, 0 }, + { "no", 253, {0, {{{0, 0}}}}, 0, 0 }, + { "lt", 254, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_cond16 = @@ -467,24 +467,24 @@ CGEN_KEYWORD m32c_cgen_opval_h_cond16 = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16c_entries[] = { - { "geu", 0, {0, {0}}, 0, 0 }, - { "c", 0, {0, {0}}, 0, 0 }, - { "gtu", 1, {0, {0}}, 0, 0 }, - { "eq", 2, {0, {0}}, 0, 0 }, - { "z", 2, {0, {0}}, 0, 0 }, - { "n", 3, {0, {0}}, 0, 0 }, - { "ltu", 4, {0, {0}}, 0, 0 }, - { "nc", 4, {0, {0}}, 0, 0 }, - { "leu", 5, {0, {0}}, 0, 0 }, - { "ne", 6, {0, {0}}, 0, 0 }, - { "nz", 6, {0, {0}}, 0, 0 }, - { "pz", 7, {0, {0}}, 0, 0 }, - { "le", 8, {0, {0}}, 0, 0 }, - { "o", 9, {0, {0}}, 0, 0 }, - { "ge", 10, {0, {0}}, 0, 0 }, - { "gt", 12, {0, {0}}, 0, 0 }, - { "no", 13, {0, {0}}, 0, 0 }, - { "lt", 14, {0, {0}}, 0, 0 } + { "geu", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "c", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "gtu", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "eq", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "z", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "n", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "ltu", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "nc", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "leu", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "ne", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "nz", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "pz", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "le", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "o", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "ge", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "gt", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "no", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "lt", 14, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_cond16c = @@ -496,12 +496,12 @@ CGEN_KEYWORD m32c_cgen_opval_h_cond16c = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16j_entries[] = { - { "le", 8, {0, {0}}, 0, 0 }, - { "o", 9, {0, {0}}, 0, 0 }, - { "ge", 10, {0, {0}}, 0, 0 }, - { "gt", 12, {0, {0}}, 0, 0 }, - { "no", 13, {0, {0}}, 0, 0 }, - { "lt", 14, {0, {0}}, 0, 0 } + { "le", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "o", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "ge", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "gt", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "no", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "lt", 14, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_cond16j = @@ -513,18 +513,18 @@ CGEN_KEYWORD m32c_cgen_opval_h_cond16j = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16j_5_entries[] = { - { "geu", 0, {0, {0}}, 0, 0 }, - { "c", 0, {0, {0}}, 0, 0 }, - { "gtu", 1, {0, {0}}, 0, 0 }, - { "eq", 2, {0, {0}}, 0, 0 }, - { "z", 2, {0, {0}}, 0, 0 }, - { "n", 3, {0, {0}}, 0, 0 }, - { "ltu", 4, {0, {0}}, 0, 0 }, - { "nc", 4, {0, {0}}, 0, 0 }, - { "leu", 5, {0, {0}}, 0, 0 }, - { "ne", 6, {0, {0}}, 0, 0 }, - { "nz", 6, {0, {0}}, 0, 0 }, - { "pz", 7, {0, {0}}, 0, 0 } + { "geu", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "c", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "gtu", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "eq", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "z", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "n", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "ltu", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "nc", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "leu", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "ne", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "nz", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "pz", 7, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_cond16j_5 = @@ -536,24 +536,24 @@ CGEN_KEYWORD m32c_cgen_opval_h_cond16j_5 = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond32_entries[] = { - { "ltu", 0, {0, {0}}, 0, 0 }, - { "nc", 0, {0, {0}}, 0, 0 }, - { "leu", 1, {0, {0}}, 0, 0 }, - { "ne", 2, {0, {0}}, 0, 0 }, - { "nz", 2, {0, {0}}, 0, 0 }, - { "pz", 3, {0, {0}}, 0, 0 }, - { "no", 4, {0, {0}}, 0, 0 }, - { "gt", 5, {0, {0}}, 0, 0 }, - { "ge", 6, {0, {0}}, 0, 0 }, - { "geu", 8, {0, {0}}, 0, 0 }, - { "c", 8, {0, {0}}, 0, 0 }, - { "gtu", 9, {0, {0}}, 0, 0 }, - { "eq", 10, {0, {0}}, 0, 0 }, - { "z", 10, {0, {0}}, 0, 0 }, - { "n", 11, {0, {0}}, 0, 0 }, - { "o", 12, {0, {0}}, 0, 0 }, - { "le", 13, {0, {0}}, 0, 0 }, - { "lt", 14, {0, {0}}, 0, 0 } + { "ltu", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "nc", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "leu", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "ne", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "nz", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "pz", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "no", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "gt", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "ge", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "geu", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "c", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "gtu", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "eq", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "z", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "n", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "o", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "le", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "lt", 14, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_cond32 = @@ -565,14 +565,14 @@ CGEN_KEYWORD m32c_cgen_opval_h_cond32 = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr1_32_entries[] = { - { "dct0", 0, {0, {0}}, 0, 0 }, - { "dct1", 1, {0, {0}}, 0, 0 }, - { "flg", 2, {0, {0}}, 0, 0 }, - { "svf", 3, {0, {0}}, 0, 0 }, - { "drc0", 4, {0, {0}}, 0, 0 }, - { "drc1", 5, {0, {0}}, 0, 0 }, - { "dmd0", 6, {0, {0}}, 0, 0 }, - { "dmd1", 7, {0, {0}}, 0, 0 } + { "dct0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "dct1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "flg", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "svf", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "drc0", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "drc1", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "dmd0", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "dmd1", 7, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_cr1_32 = @@ -584,13 +584,13 @@ CGEN_KEYWORD m32c_cgen_opval_h_cr1_32 = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr2_32_entries[] = { - { "intb", 0, {0, {0}}, 0, 0 }, - { "sp", 1, {0, {0}}, 0, 0 }, - { "sb", 2, {0, {0}}, 0, 0 }, - { "fb", 3, {0, {0}}, 0, 0 }, - { "svp", 4, {0, {0}}, 0, 0 }, - { "vct", 5, {0, {0}}, 0, 0 }, - { "isp", 7, {0, {0}}, 0, 0 } + { "intb", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "sp", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "sb", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "fb", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "svp", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "vct", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "isp", 7, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_cr2_32 = @@ -602,12 +602,12 @@ CGEN_KEYWORD m32c_cgen_opval_h_cr2_32 = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr3_32_entries[] = { - { "dma0", 2, {0, {0}}, 0, 0 }, - { "dma1", 3, {0, {0}}, 0, 0 }, - { "dra0", 4, {0, {0}}, 0, 0 }, - { "dra1", 5, {0, {0}}, 0, 0 }, - { "dsa0", 6, {0, {0}}, 0, 0 }, - { "dsa1", 7, {0, {0}}, 0, 0 } + { "dma0", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "dma1", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "dra0", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "dra1", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "dsa0", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "dsa1", 7, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_cr3_32 = @@ -619,13 +619,13 @@ CGEN_KEYWORD m32c_cgen_opval_h_cr3_32 = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr_16_entries[] = { - { "intbl", 1, {0, {0}}, 0, 0 }, - { "intbh", 2, {0, {0}}, 0, 0 }, - { "flg", 3, {0, {0}}, 0, 0 }, - { "isp", 4, {0, {0}}, 0, 0 }, - { "sp", 5, {0, {0}}, 0, 0 }, - { "sb", 6, {0, {0}}, 0, 0 }, - { "fb", 7, {0, {0}}, 0, 0 } + { "intbl", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "intbh", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "flg", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "isp", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "sp", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "sb", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "fb", 7, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_cr_16 = @@ -637,14 +637,14 @@ CGEN_KEYWORD m32c_cgen_opval_h_cr_16 = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_flags_entries[] = { - { "c", 0, {0, {0}}, 0, 0 }, - { "d", 1, {0, {0}}, 0, 0 }, - { "z", 2, {0, {0}}, 0, 0 }, - { "s", 3, {0, {0}}, 0, 0 }, - { "b", 4, {0, {0}}, 0, 0 }, - { "o", 5, {0, {0}}, 0, 0 }, - { "i", 6, {0, {0}}, 0, 0 }, - { "u", 7, {0, {0}}, 0, 0 } + { "c", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "d", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "z", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "s", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "b", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "o", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "i", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "u", 7, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_flags = @@ -656,22 +656,22 @@ CGEN_KEYWORD m32c_cgen_opval_h_flags = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_shimm_entries[] = { - { "1", 0, {0, {0}}, 0, 0 }, - { "2", 1, {0, {0}}, 0, 0 }, - { "3", 2, {0, {0}}, 0, 0 }, - { "4", 3, {0, {0}}, 0, 0 }, - { "5", 4, {0, {0}}, 0, 0 }, - { "6", 5, {0, {0}}, 0, 0 }, - { "7", 6, {0, {0}}, 0, 0 }, - { "8", 7, {0, {0}}, 0, 0 }, - { "-1", -8, {0, {0}}, 0, 0 }, - { "-2", -7, {0, {0}}, 0, 0 }, - { "-3", -6, {0, {0}}, 0, 0 }, - { "-4", -5, {0, {0}}, 0, 0 }, - { "-5", -4, {0, {0}}, 0, 0 }, - { "-6", -3, {0, {0}}, 0, 0 }, - { "-7", -2, {0, {0}}, 0, 0 }, - { "-8", -1, {0, {0}}, 0, 0 } + { "1", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "2", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "3", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "4", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "5", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "6", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "7", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "8", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "-1", -8, {0, {{{0, 0}}}}, 0, 0 }, + { "-2", -7, {0, {{{0, 0}}}}, 0, 0 }, + { "-3", -6, {0, {{{0, 0}}}}, 0, 0 }, + { "-4", -5, {0, {{{0, 0}}}}, 0, 0 }, + { "-5", -4, {0, {{{0, 0}}}}, 0, 0 }, + { "-6", -3, {0, {{{0, 0}}}}, 0, 0 }, + { "-7", -2, {0, {{{0, 0}}}}, 0, 0 }, + { "-8", -1, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_shimm = @@ -692,82 +692,82 @@ CGEN_KEYWORD m32c_cgen_opval_h_shimm = const CGEN_HW_ENTRY m32c_cgen_hw_table[] = { - { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<isas; + CGEN_BITSET *isas = cd->isas; unsigned int machs = cd->machs; cd->int_insn_p = CGEN_INT_INSN_P; @@ -62798,7 +62798,7 @@ m32c_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ cd->max_insn_bitsize = 0; for (i = 0; i < MAX_ISAS; ++i) - if (((1 << i) & isas) != 0) + if (cgen_bitset_contains (isas, i)) { const CGEN_ISA *isa = & m32c_cgen_isa_table[i]; @@ -62883,7 +62883,7 @@ m32c_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) { CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); static int init_p; - unsigned int isas = 0; /* 0 = "unspecified" */ + CGEN_BITSET *isas = 0; /* 0 = "unspecified" */ unsigned int machs = 0; /* 0 = "unspecified" */ enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; va_list ap; @@ -62902,7 +62902,7 @@ m32c_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) switch (arg_type) { case CGEN_CPU_OPEN_ISAS : - isas = va_arg (ap, unsigned int); + isas = va_arg (ap, CGEN_BITSET *); break; case CGEN_CPU_OPEN_MACHS : machs = va_arg (ap, unsigned int); @@ -62933,9 +62933,6 @@ m32c_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) machs = (1 << MAX_MACHS) - 1; /* Base mach is always selected. */ machs |= 1; - /* ISA unspecified means "all". */ - if (isas == 0) - isas = (1 << MAX_ISAS) - 1; if (endian == CGEN_ENDIAN_UNKNOWN) { /* ??? If target has only one, could have a default. */ @@ -62943,7 +62940,7 @@ m32c_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) abort (); } - cd->isas = isas; + cd->isas = cgen_bitset_copy (isas); cd->machs = machs; cd->endian = endian; /* FIXME: for the sparc case we can determine insn-endianness statically. diff --git a/opcodes/m32c-desc.h b/opcodes/m32c-desc.h index b969707..3fa1db9 100644 --- a/opcodes/m32c-desc.h +++ b/opcodes/m32c-desc.h @@ -25,6 +25,8 @@ with this program; if not, write to the Free Software Foundation, Inc., #ifndef M32C_CPU_H #define M32C_CPU_H +#include "opcode/cgen-bitset.h" + #define CGEN_ARCH m32c /* Given symbol S, return m32c_cgen_. */ @@ -92,6 +94,16 @@ typedef enum cgen_ifld_attr { /* Number of non-boolean elements in cgen_ifld_attr. */ #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) +/* cgen_ifld attribute accessor macros. */ +#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_IFLD_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_ISA-CGEN_IFLD_START_NBOOLS-1].bitset) +#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0) + /* Enum declaration for m32c ifield types. */ typedef enum ifield_type { M32C_F_NIL, M32C_F_ANYOF, M32C_F_0_1, M32C_F_0_2 @@ -150,6 +162,14 @@ typedef enum cgen_hw_attr { /* Number of non-boolean elements in cgen_hw_attr. */ #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) +/* cgen_hw attribute accessor macros. */ +#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_HW_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_ISA-CGEN_HW_START_NBOOLS-1].bitset) +#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0) +#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0) +#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0) + /* Enum declaration for m32c hardware types. */ typedef enum cgen_hw_type { HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR @@ -188,6 +208,18 @@ typedef enum cgen_operand_attr { /* Number of non-boolean elements in cgen_operand_attr. */ #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) +/* cgen_operand attribute accessor macros. */ +#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_OPERAND_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_ISA-CGEN_OPERAND_START_NBOOLS-1].bitset) +#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) + /* Enum declaration for m32c operand types. */ typedef enum cgen_operand_type { M32C_OPERAND_PC, M32C_OPERAND_SRC16RNQI, M32C_OPERAND_SRC16RNHI, M32C_OPERAND_SRC32RNUNPREFIXEDQI @@ -430,6 +462,20 @@ typedef enum cgen_insn_attr { /* Number of non-boolean elements in cgen_insn_attr. */ #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) +/* cgen_insn attribute accessor macros. */ +#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_ISA-CGEN_INSN_START_NBOOLS-1].bitset) +#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0) +#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0) +#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0) +#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0) + /* cgen.h uses things we just defined. */ #include "opcode/cgen.h" diff --git a/opcodes/m32c-dis.c b/opcodes/m32c-dis.c index cfa3517..43f93e2 100644 --- a/opcodes/m32c-dis.c +++ b/opcodes/m32c-dis.c @@ -4,7 +4,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. - the resultant file is machine generated, cgen-dis.in isn't - Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005 + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005 Free Software Foundation, Inc. This file is part of the GNU Binutils and GDB, the GNU debugger. @@ -1190,7 +1190,7 @@ default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) typedef struct cpu_desc_list { struct cpu_desc_list *next; - int isa; + CGEN_BITSET *isa; int mach; int endian; CGEN_CPU_DESC cd; @@ -1202,11 +1202,12 @@ print_insn_m32c (bfd_vma pc, disassemble_info *info) static cpu_desc_list *cd_list = 0; cpu_desc_list *cl = 0; static CGEN_CPU_DESC cd = 0; - static int prev_isa; + static CGEN_BITSET *prev_isa; static int prev_mach; static int prev_endian; int length; - int isa,mach; + CGEN_BITSET *isa; + int mach; int endian = (info->endian == BFD_ENDIAN_BIG ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE); @@ -1229,25 +1230,34 @@ print_insn_m32c (bfd_vma pc, disassemble_info *info) #endif #ifdef CGEN_COMPUTE_ISA - isa = CGEN_COMPUTE_ISA (info); + { + static CGEN_BITSET *permanent_isa; + + if (!permanent_isa) + permanent_isa = cgen_bitset_create (MAX_ISAS); + isa = permanent_isa; + cgen_bitset_clear (isa); + cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info)); + } #else isa = info->insn_sets; #endif /* If we've switched cpu's, try to find a handle we've used before */ if (cd - && (isa != prev_isa + && (cgen_bitset_compare (isa, prev_isa) != 0 || mach != prev_mach || endian != prev_endian)) { cd = 0; for (cl = cd_list; cl; cl = cl->next) { - if (cl->isa == isa && + if (cgen_bitset_compare (cl->isa, isa) == 0 && cl->mach == mach && cl->endian == endian) { cd = cl->cd; + prev_isa = cd->isas; break; } } @@ -1263,7 +1273,7 @@ print_insn_m32c (bfd_vma pc, disassemble_info *info) abort (); mach_name = arch_type->printable_name; - prev_isa = isa; + prev_isa = cgen_bitset_copy (isa); prev_mach = mach; prev_endian = endian; cd = m32c_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, @@ -1276,7 +1286,7 @@ print_insn_m32c (bfd_vma pc, disassemble_info *info) /* Save this away for future reference. */ cl = xmalloc (sizeof (struct cpu_desc_list)); cl->cd = cd; - cl->isa = isa; + cl->isa = prev_isa; cl->mach = mach; cl->endian = endian; cl->next = cd_list; diff --git a/opcodes/m32c-opc.c b/opcodes/m32c-opc.c index 185abad..0913c2c 100644 --- a/opcodes/m32c-opc.c +++ b/opcodes/m32c-opc.c @@ -79916,7 +79916,7 @@ static const CGEN_IBASE m32c_cgen_macro_insn_table[] = /* add.b:q #${Imm-12-s4},sp */ { -1, "add16-bQ-sp", "add.b:q", 16, - { 0|A(ALIAS), { (1<isas; + CGEN_BITSET *isas = cd->isas; unsigned int machs = cd->machs; cd->int_insn_p = CGEN_INT_INSN_P; @@ -1336,7 +1336,7 @@ m32r_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ cd->max_insn_bitsize = 0; for (i = 0; i < MAX_ISAS; ++i) - if (((1 << i) & isas) != 0) + if (cgen_bitset_contains (isas, i)) { const CGEN_ISA *isa = & m32r_cgen_isa_table[i]; @@ -1421,7 +1421,7 @@ m32r_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) { CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); static int init_p; - unsigned int isas = 0; /* 0 = "unspecified" */ + CGEN_BITSET *isas = 0; /* 0 = "unspecified" */ unsigned int machs = 0; /* 0 = "unspecified" */ enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; va_list ap; @@ -1440,7 +1440,7 @@ m32r_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) switch (arg_type) { case CGEN_CPU_OPEN_ISAS : - isas = va_arg (ap, unsigned int); + isas = va_arg (ap, CGEN_BITSET *); break; case CGEN_CPU_OPEN_MACHS : machs = va_arg (ap, unsigned int); @@ -1471,9 +1471,6 @@ m32r_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) machs = (1 << MAX_MACHS) - 1; /* Base mach is always selected. */ machs |= 1; - /* ISA unspecified means "all". */ - if (isas == 0) - isas = (1 << MAX_ISAS) - 1; if (endian == CGEN_ENDIAN_UNKNOWN) { /* ??? If target has only one, could have a default. */ @@ -1481,7 +1478,7 @@ m32r_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) abort (); } - cd->isas = isas; + cd->isas = cgen_bitset_copy (isas); cd->machs = machs; cd->endian = endian; /* FIXME: for the sparc case we can determine insn-endianness statically. diff --git a/opcodes/m32r-desc.h b/opcodes/m32r-desc.h index 2080b5c..9624852 100644 --- a/opcodes/m32r-desc.h +++ b/opcodes/m32r-desc.h @@ -25,6 +25,8 @@ with this program; if not, write to the Free Software Foundation, Inc., #ifndef M32R_CPU_H #define M32R_CPU_H +#include "opcode/cgen-bitset.h" + #define CGEN_ARCH m32r /* Given symbol S, return m32r_cgen_. */ @@ -135,6 +137,16 @@ typedef enum cgen_ifld_attr { /* Number of non-boolean elements in cgen_ifld_attr. */ #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) +/* cgen_ifld attribute accessor macros. */ +#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0) +#define CGEN_ATTR_CGEN_IFLD_RELOC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RELOC)) != 0) + /* Enum declaration for m32r ifield types. */ typedef enum ifield_type { M32R_F_NIL, M32R_F_ANYOF, M32R_F_OP1, M32R_F_OP2 @@ -160,6 +172,13 @@ typedef enum cgen_hw_attr { /* Number of non-boolean elements in cgen_hw_attr. */ #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) +/* cgen_hw attribute accessor macros. */ +#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0) +#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0) +#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0) + /* Enum declaration for m32r hardware types. */ typedef enum cgen_hw_type { HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR @@ -184,6 +203,19 @@ typedef enum cgen_operand_attr { /* Number of non-boolean elements in cgen_operand_attr. */ #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) +/* cgen_operand attribute accessor macros. */ +#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_RELOC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELOC)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_HASH_PREFIX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_HASH_PREFIX)) != 0) + /* Enum declaration for m32r operand types. */ typedef enum cgen_operand_type { M32R_OPERAND_PC, M32R_OPERAND_SR, M32R_OPERAND_DR, M32R_OPERAND_SRC1 @@ -216,6 +248,24 @@ typedef enum cgen_insn_attr { /* Number of non-boolean elements in cgen_insn_attr. */ #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) +/* cgen_insn attribute accessor macros. */ +#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_PIPE_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_PIPE-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0) +#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0) +#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0) +#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0) +#define CGEN_ATTR_CGEN_INSN_FILL_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_FILL_SLOT)) != 0) +#define CGEN_ATTR_CGEN_INSN_SPECIAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SPECIAL)) != 0) +#define CGEN_ATTR_CGEN_INSN_SPECIAL_M32R_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SPECIAL_M32R)) != 0) +#define CGEN_ATTR_CGEN_INSN_SPECIAL_FLOAT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SPECIAL_FLOAT)) != 0) + /* cgen.h uses things we just defined. */ #include "opcode/cgen.h" diff --git a/opcodes/m32r-dis.c b/opcodes/m32r-dis.c index fb65bfe..e381c919 100644 --- a/opcodes/m32r-dis.c +++ b/opcodes/m32r-dis.c @@ -4,7 +4,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. - the resultant file is machine generated, cgen-dis.in isn't - Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005 + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005 Free Software Foundation, Inc. This file is part of the GNU Binutils and GDB, the GNU debugger. @@ -564,7 +564,7 @@ default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) typedef struct cpu_desc_list { struct cpu_desc_list *next; - int isa; + CGEN_BITSET *isa; int mach; int endian; CGEN_CPU_DESC cd; @@ -576,11 +576,12 @@ print_insn_m32r (bfd_vma pc, disassemble_info *info) static cpu_desc_list *cd_list = 0; cpu_desc_list *cl = 0; static CGEN_CPU_DESC cd = 0; - static int prev_isa; + static CGEN_BITSET *prev_isa; static int prev_mach; static int prev_endian; int length; - int isa,mach; + CGEN_BITSET *isa; + int mach; int endian = (info->endian == BFD_ENDIAN_BIG ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE); @@ -603,25 +604,34 @@ print_insn_m32r (bfd_vma pc, disassemble_info *info) #endif #ifdef CGEN_COMPUTE_ISA - isa = CGEN_COMPUTE_ISA (info); + { + static CGEN_BITSET *permanent_isa; + + if (!permanent_isa) + permanent_isa = cgen_bitset_create (MAX_ISAS); + isa = permanent_isa; + cgen_bitset_clear (isa); + cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info)); + } #else isa = info->insn_sets; #endif /* If we've switched cpu's, try to find a handle we've used before */ if (cd - && (isa != prev_isa + && (cgen_bitset_compare (isa, prev_isa) != 0 || mach != prev_mach || endian != prev_endian)) { cd = 0; for (cl = cd_list; cl; cl = cl->next) { - if (cl->isa == isa && + if (cgen_bitset_compare (cl->isa, isa) == 0 && cl->mach == mach && cl->endian == endian) { cd = cl->cd; + prev_isa = cd->isas; break; } } @@ -637,7 +647,7 @@ print_insn_m32r (bfd_vma pc, disassemble_info *info) abort (); mach_name = arch_type->printable_name; - prev_isa = isa; + prev_isa = cgen_bitset_copy (isa); prev_mach = mach; prev_endian = endian; cd = m32r_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, @@ -650,7 +660,7 @@ print_insn_m32r (bfd_vma pc, disassemble_info *info) /* Save this away for future reference. */ cl = xmalloc (sizeof (struct cpu_desc_list)); cl->cd = cd; - cl->isa = isa; + cl->isa = prev_isa; cl->mach = mach; cl->endian = endian; cl->next = cd_list; diff --git a/opcodes/m32r-opc.c b/opcodes/m32r-opc.c index 29b7a21..7669eb6 100644 --- a/opcodes/m32r-opc.c +++ b/opcodes/m32r-opc.c @@ -1301,182 +1301,182 @@ static const CGEN_IBASE m32r_cgen_macro_insn_table[] = /* bc $disp8 */ { -1, "bc8r", "bc", 16, - { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<isas; + CGEN_BITSET *isas = cd->isas; unsigned int machs = cd->machs; cd->int_insn_p = CGEN_INT_INSN_P; @@ -1046,7 +1046,7 @@ ms1_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ cd->max_insn_bitsize = 0; for (i = 0; i < MAX_ISAS; ++i) - if (((1 << i) & isas) != 0) + if (cgen_bitset_contains (isas, i)) { const CGEN_ISA *isa = & ms1_cgen_isa_table[i]; @@ -1131,7 +1131,7 @@ ms1_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) { CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); static int init_p; - unsigned int isas = 0; /* 0 = "unspecified" */ + CGEN_BITSET *isas = 0; /* 0 = "unspecified" */ unsigned int machs = 0; /* 0 = "unspecified" */ enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; va_list ap; @@ -1150,7 +1150,7 @@ ms1_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) switch (arg_type) { case CGEN_CPU_OPEN_ISAS : - isas = va_arg (ap, unsigned int); + isas = va_arg (ap, CGEN_BITSET *); break; case CGEN_CPU_OPEN_MACHS : machs = va_arg (ap, unsigned int); @@ -1181,9 +1181,6 @@ ms1_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) machs = (1 << MAX_MACHS) - 1; /* Base mach is always selected. */ machs |= 1; - /* ISA unspecified means "all". */ - if (isas == 0) - isas = (1 << MAX_ISAS) - 1; if (endian == CGEN_ENDIAN_UNKNOWN) { /* ??? If target has only one, could have a default. */ @@ -1191,7 +1188,7 @@ ms1_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) abort (); } - cd->isas = isas; + cd->isas = cgen_bitset_copy (isas); cd->machs = machs; cd->endian = endian; /* FIXME: for the sparc case we can determine insn-endianness statically. diff --git a/opcodes/ms1-desc.h b/opcodes/ms1-desc.h index 9dfd4da..4a3dd2f 100644 --- a/opcodes/ms1-desc.h +++ b/opcodes/ms1-desc.h @@ -25,6 +25,8 @@ with this program; if not, write to the Free Software Foundation, Inc., #ifndef MS1_CPU_H #define MS1_CPU_H +#include "opcode/cgen-bitset.h" + #define CGEN_ARCH ms1 /* Given symbol S, return ms1_cgen_. */ @@ -131,6 +133,15 @@ typedef enum cgen_ifld_attr { /* Number of non-boolean elements in cgen_ifld_attr. */ #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) +/* cgen_ifld attribute accessor macros. */ +#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0) + /* Enum declaration for ms1 ifield types. */ typedef enum ifield_type { MS1_F_NIL, MS1_F_ANYOF, MS1_F_MSYS, MS1_F_OPC @@ -166,6 +177,13 @@ typedef enum cgen_hw_attr { /* Number of non-boolean elements in cgen_hw_attr. */ #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) +/* cgen_hw attribute accessor macros. */ +#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0) +#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0) +#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0) + /* Enum declaration for ms1 hardware types. */ typedef enum cgen_hw_type { HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR @@ -186,6 +204,17 @@ typedef enum cgen_operand_attr { /* Number of non-boolean elements in cgen_operand_attr. */ #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) +/* cgen_operand attribute accessor macros. */ +#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) + /* Enum declaration for ms1 operand types. */ typedef enum cgen_operand_type { MS1_OPERAND_PC, MS1_OPERAND_FRSR1, MS1_OPERAND_FRSR2, MS1_OPERAND_FRDR @@ -224,6 +253,29 @@ typedef enum cgen_insn_attr { /* Number of non-boolean elements in cgen_insn_attr. */ #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) +/* cgen_insn attribute accessor macros. */ +#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0) +#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0) +#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0) +#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0) +#define CGEN_ATTR_CGEN_INSN_LOAD_DELAY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_LOAD_DELAY)) != 0) +#define CGEN_ATTR_CGEN_INSN_MEMORY_ACCESS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_MEMORY_ACCESS)) != 0) +#define CGEN_ATTR_CGEN_INSN_AL_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_AL_INSN)) != 0) +#define CGEN_ATTR_CGEN_INSN_IO_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_IO_INSN)) != 0) +#define CGEN_ATTR_CGEN_INSN_BR_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_BR_INSN)) != 0) +#define CGEN_ATTR_CGEN_INSN_USES_FRDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_USES_FRDR)) != 0) +#define CGEN_ATTR_CGEN_INSN_USES_FRDRRR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_USES_FRDRRR)) != 0) +#define CGEN_ATTR_CGEN_INSN_USES_FRSR1_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_USES_FRSR1)) != 0) +#define CGEN_ATTR_CGEN_INSN_USES_FRSR2_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_USES_FRSR2)) != 0) +#define CGEN_ATTR_CGEN_INSN_SKIPA_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIPA)) != 0) + /* cgen.h uses things we just defined. */ #include "opcode/cgen.h" diff --git a/opcodes/ms1-dis.c b/opcodes/ms1-dis.c index 980e8e0..0026124 100644 --- a/opcodes/ms1-dis.c +++ b/opcodes/ms1-dis.c @@ -4,7 +4,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. - the resultant file is machine generated, cgen-dis.in isn't - Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005 + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005 Free Software Foundation, Inc. This file is part of the GNU Binutils and GDB, the GNU debugger. @@ -566,7 +566,7 @@ default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) typedef struct cpu_desc_list { struct cpu_desc_list *next; - int isa; + CGEN_BITSET *isa; int mach; int endian; CGEN_CPU_DESC cd; @@ -578,11 +578,12 @@ print_insn_ms1 (bfd_vma pc, disassemble_info *info) static cpu_desc_list *cd_list = 0; cpu_desc_list *cl = 0; static CGEN_CPU_DESC cd = 0; - static int prev_isa; + static CGEN_BITSET *prev_isa; static int prev_mach; static int prev_endian; int length; - int isa,mach; + CGEN_BITSET *isa; + int mach; int endian = (info->endian == BFD_ENDIAN_BIG ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE); @@ -605,25 +606,34 @@ print_insn_ms1 (bfd_vma pc, disassemble_info *info) #endif #ifdef CGEN_COMPUTE_ISA - isa = CGEN_COMPUTE_ISA (info); + { + static CGEN_BITSET *permanent_isa; + + if (!permanent_isa) + permanent_isa = cgen_bitset_create (MAX_ISAS); + isa = permanent_isa; + cgen_bitset_clear (isa); + cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info)); + } #else isa = info->insn_sets; #endif /* If we've switched cpu's, try to find a handle we've used before */ if (cd - && (isa != prev_isa + && (cgen_bitset_compare (isa, prev_isa) != 0 || mach != prev_mach || endian != prev_endian)) { cd = 0; for (cl = cd_list; cl; cl = cl->next) { - if (cl->isa == isa && + if (cgen_bitset_compare (cl->isa, isa) == 0 && cl->mach == mach && cl->endian == endian) { cd = cl->cd; + prev_isa = cd->isas; break; } } @@ -639,7 +649,7 @@ print_insn_ms1 (bfd_vma pc, disassemble_info *info) abort (); mach_name = arch_type->printable_name; - prev_isa = isa; + prev_isa = cgen_bitset_copy (isa); prev_mach = mach; prev_endian = endian; cd = ms1_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, @@ -652,7 +662,7 @@ print_insn_ms1 (bfd_vma pc, disassemble_info *info) /* Save this away for future reference. */ cl = xmalloc (sizeof (struct cpu_desc_list)); cl->cd = cd; - cl->isa = isa; + cl->isa = prev_isa; cl->mach = mach; cl->endian = endian; cl->next = cd_list; diff --git a/opcodes/openrisc-desc.c b/opcodes/openrisc-desc.c index c469694..5bdbeca 100644 --- a/opcodes/openrisc-desc.c +++ b/opcodes/openrisc-desc.c @@ -136,41 +136,41 @@ static const CGEN_MACH openrisc_cgen_mach_table[] = { static CGEN_KEYWORD_ENTRY openrisc_cgen_opval_h_gr_entries[] = { - { "r0", 0, {0, {0}}, 0, 0 }, - { "r1", 1, {0, {0}}, 0, 0 }, - { "r2", 2, {0, {0}}, 0, 0 }, - { "r3", 3, {0, {0}}, 0, 0 }, - { "r4", 4, {0, {0}}, 0, 0 }, - { "r5", 5, {0, {0}}, 0, 0 }, - { "r6", 6, {0, {0}}, 0, 0 }, - { "r7", 7, {0, {0}}, 0, 0 }, - { "r8", 8, {0, {0}}, 0, 0 }, - { "r9", 9, {0, {0}}, 0, 0 }, - { "r10", 10, {0, {0}}, 0, 0 }, - { "r11", 11, {0, {0}}, 0, 0 }, - { "r12", 12, {0, {0}}, 0, 0 }, - { "r13", 13, {0, {0}}, 0, 0 }, - { "r14", 14, {0, {0}}, 0, 0 }, - { "r15", 15, {0, {0}}, 0, 0 }, - { "r16", 16, {0, {0}}, 0, 0 }, - { "r17", 17, {0, {0}}, 0, 0 }, - { "r18", 18, {0, {0}}, 0, 0 }, - { "r19", 19, {0, {0}}, 0, 0 }, - { "r20", 20, {0, {0}}, 0, 0 }, - { "r21", 21, {0, {0}}, 0, 0 }, - { "r22", 22, {0, {0}}, 0, 0 }, - { "r23", 23, {0, {0}}, 0, 0 }, - { "r24", 24, {0, {0}}, 0, 0 }, - { "r25", 25, {0, {0}}, 0, 0 }, - { "r26", 26, {0, {0}}, 0, 0 }, - { "r27", 27, {0, {0}}, 0, 0 }, - { "r28", 28, {0, {0}}, 0, 0 }, - { "r29", 29, {0, {0}}, 0, 0 }, - { "r30", 30, {0, {0}}, 0, 0 }, - { "r31", 31, {0, {0}}, 0, 0 }, - { "lr", 11, {0, {0}}, 0, 0 }, - { "sp", 1, {0, {0}}, 0, 0 }, - { "fp", 2, {0, {0}}, 0, 0 } + { "r0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "r1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "r2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "r3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "r4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "r5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "r6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "r7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "r8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "r9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "r10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "r11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "r12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "r13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "r14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "r15", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "r16", 16, {0, {{{0, 0}}}}, 0, 0 }, + { "r17", 17, {0, {{{0, 0}}}}, 0, 0 }, + { "r18", 18, {0, {{{0, 0}}}}, 0, 0 }, + { "r19", 19, {0, {{{0, 0}}}}, 0, 0 }, + { "r20", 20, {0, {{{0, 0}}}}, 0, 0 }, + { "r21", 21, {0, {{{0, 0}}}}, 0, 0 }, + { "r22", 22, {0, {{{0, 0}}}}, 0, 0 }, + { "r23", 23, {0, {{{0, 0}}}}, 0, 0 }, + { "r24", 24, {0, {{{0, 0}}}}, 0, 0 }, + { "r25", 25, {0, {{{0, 0}}}}, 0, 0 }, + { "r26", 26, {0, {{{0, 0}}}}, 0, 0 }, + { "r27", 27, {0, {{{0, 0}}}}, 0, 0 }, + { "r28", 28, {0, {{{0, 0}}}}, 0, 0 }, + { "r29", 29, {0, {{{0, 0}}}}, 0, 0 }, + { "r30", 30, {0, {{{0, 0}}}}, 0, 0 }, + { "r31", 31, {0, {{{0, 0}}}}, 0, 0 }, + { "lr", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "sp", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "fp", 2, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD openrisc_cgen_opval_h_gr = @@ -191,19 +191,19 @@ CGEN_KEYWORD openrisc_cgen_opval_h_gr = const CGEN_HW_ENTRY openrisc_cgen_hw_table[] = { - { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<isas; + CGEN_BITSET *isas = cd->isas; unsigned int machs = cd->machs; cd->int_insn_p = CGEN_INT_INSN_P; @@ -826,7 +826,7 @@ openrisc_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ cd->max_insn_bitsize = 0; for (i = 0; i < MAX_ISAS; ++i) - if (((1 << i) & isas) != 0) + if (cgen_bitset_contains (isas, i)) { const CGEN_ISA *isa = & openrisc_cgen_isa_table[i]; @@ -911,7 +911,7 @@ openrisc_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) { CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); static int init_p; - unsigned int isas = 0; /* 0 = "unspecified" */ + CGEN_BITSET *isas = 0; /* 0 = "unspecified" */ unsigned int machs = 0; /* 0 = "unspecified" */ enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; va_list ap; @@ -930,7 +930,7 @@ openrisc_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) switch (arg_type) { case CGEN_CPU_OPEN_ISAS : - isas = va_arg (ap, unsigned int); + isas = va_arg (ap, CGEN_BITSET *); break; case CGEN_CPU_OPEN_MACHS : machs = va_arg (ap, unsigned int); @@ -961,9 +961,6 @@ openrisc_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) machs = (1 << MAX_MACHS) - 1; /* Base mach is always selected. */ machs |= 1; - /* ISA unspecified means "all". */ - if (isas == 0) - isas = (1 << MAX_ISAS) - 1; if (endian == CGEN_ENDIAN_UNKNOWN) { /* ??? If target has only one, could have a default. */ @@ -971,7 +968,7 @@ openrisc_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) abort (); } - cd->isas = isas; + cd->isas = cgen_bitset_copy (isas); cd->machs = machs; cd->endian = endian; /* FIXME: for the sparc case we can determine insn-endianness statically. diff --git a/opcodes/openrisc-desc.h b/opcodes/openrisc-desc.h index b47da96..dd0ccf8 100644 --- a/opcodes/openrisc-desc.h +++ b/opcodes/openrisc-desc.h @@ -25,6 +25,8 @@ with this program; if not, write to the Free Software Foundation, Inc., #ifndef OPENRISC_CPU_H #define OPENRISC_CPU_H +#include "opcode/cgen-bitset.h" + #define CGEN_ARCH openrisc /* Given symbol S, return openrisc_cgen_. */ @@ -154,6 +156,15 @@ typedef enum cgen_ifld_attr { /* Number of non-boolean elements in cgen_ifld_attr. */ #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) +/* cgen_ifld attribute accessor macros. */ +#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0) + /* Enum declaration for openrisc ifield types. */ typedef enum ifield_type { OPENRISC_F_NIL, OPENRISC_F_ANYOF, OPENRISC_F_CLASS, OPENRISC_F_SUB @@ -179,6 +190,13 @@ typedef enum cgen_hw_attr { /* Number of non-boolean elements in cgen_hw_attr. */ #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) +/* cgen_hw attribute accessor macros. */ +#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0) +#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0) +#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0) + /* Enum declaration for openrisc hardware types. */ typedef enum cgen_hw_type { HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR @@ -201,6 +219,17 @@ typedef enum cgen_operand_attr { /* Number of non-boolean elements in cgen_operand_attr. */ #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) +/* cgen_operand attribute accessor macros. */ +#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) + /* Enum declaration for openrisc operand types. */ typedef enum cgen_operand_type { OPENRISC_OPERAND_PC, OPENRISC_OPERAND_SR, OPENRISC_OPERAND_CBIT, OPENRISC_OPERAND_SIMM_16 @@ -229,6 +258,20 @@ typedef enum cgen_insn_attr { /* Number of non-boolean elements in cgen_insn_attr. */ #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) +/* cgen_insn attribute accessor macros. */ +#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0) +#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0) +#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0) +#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0) +#define CGEN_ATTR_CGEN_INSN_NOT_IN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NOT_IN_DELAY_SLOT)) != 0) + /* cgen.h uses things we just defined. */ #include "opcode/cgen.h" diff --git a/opcodes/openrisc-dis.c b/opcodes/openrisc-dis.c index cb3f99b..d3c4f68 100644 --- a/opcodes/openrisc-dis.c +++ b/opcodes/openrisc-dis.c @@ -4,7 +4,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. - the resultant file is machine generated, cgen-dis.in isn't - Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005 + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005 Free Software Foundation, Inc. This file is part of the GNU Binutils and GDB, the GNU debugger. @@ -443,7 +443,7 @@ default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) typedef struct cpu_desc_list { struct cpu_desc_list *next; - int isa; + CGEN_BITSET *isa; int mach; int endian; CGEN_CPU_DESC cd; @@ -455,11 +455,12 @@ print_insn_openrisc (bfd_vma pc, disassemble_info *info) static cpu_desc_list *cd_list = 0; cpu_desc_list *cl = 0; static CGEN_CPU_DESC cd = 0; - static int prev_isa; + static CGEN_BITSET *prev_isa; static int prev_mach; static int prev_endian; int length; - int isa,mach; + CGEN_BITSET *isa; + int mach; int endian = (info->endian == BFD_ENDIAN_BIG ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE); @@ -482,25 +483,34 @@ print_insn_openrisc (bfd_vma pc, disassemble_info *info) #endif #ifdef CGEN_COMPUTE_ISA - isa = CGEN_COMPUTE_ISA (info); + { + static CGEN_BITSET *permanent_isa; + + if (!permanent_isa) + permanent_isa = cgen_bitset_create (MAX_ISAS); + isa = permanent_isa; + cgen_bitset_clear (isa); + cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info)); + } #else isa = info->insn_sets; #endif /* If we've switched cpu's, try to find a handle we've used before */ if (cd - && (isa != prev_isa + && (cgen_bitset_compare (isa, prev_isa) != 0 || mach != prev_mach || endian != prev_endian)) { cd = 0; for (cl = cd_list; cl; cl = cl->next) { - if (cl->isa == isa && + if (cgen_bitset_compare (cl->isa, isa) == 0 && cl->mach == mach && cl->endian == endian) { cd = cl->cd; + prev_isa = cd->isas; break; } } @@ -516,7 +526,7 @@ print_insn_openrisc (bfd_vma pc, disassemble_info *info) abort (); mach_name = arch_type->printable_name; - prev_isa = isa; + prev_isa = cgen_bitset_copy (isa); prev_mach = mach; prev_endian = endian; cd = openrisc_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, @@ -529,7 +539,7 @@ print_insn_openrisc (bfd_vma pc, disassemble_info *info) /* Save this away for future reference. */ cl = xmalloc (sizeof (struct cpu_desc_list)); cl->cd = cd; - cl->isa = isa; + cl->isa = prev_isa; cl->mach = mach; cl->endian = endian; cl->next = cd_list; diff --git a/opcodes/openrisc-opc.c b/opcodes/openrisc-opc.c index 58aed98..ff9d52c 100644 --- a/opcodes/openrisc-opc.c +++ b/opcodes/openrisc-opc.c @@ -560,7 +560,7 @@ static const CGEN_IBASE openrisc_cgen_macro_insn_table[] = /* l.ret */ { -1, "l-ret", "l.ret", 32, - { 0|A(ALIAS), { (1<isas; + CGEN_BITSET *isas = cd->isas; unsigned int machs = cd->machs; cd->int_insn_p = CGEN_INT_INSN_P; @@ -1287,7 +1287,7 @@ xstormy16_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ cd->max_insn_bitsize = 0; for (i = 0; i < MAX_ISAS; ++i) - if (((1 << i) & isas) != 0) + if (cgen_bitset_contains (isas, i)) { const CGEN_ISA *isa = & xstormy16_cgen_isa_table[i]; @@ -1372,7 +1372,7 @@ xstormy16_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) { CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); static int init_p; - unsigned int isas = 0; /* 0 = "unspecified" */ + CGEN_BITSET *isas = 0; /* 0 = "unspecified" */ unsigned int machs = 0; /* 0 = "unspecified" */ enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; va_list ap; @@ -1391,7 +1391,7 @@ xstormy16_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) switch (arg_type) { case CGEN_CPU_OPEN_ISAS : - isas = va_arg (ap, unsigned int); + isas = va_arg (ap, CGEN_BITSET *); break; case CGEN_CPU_OPEN_MACHS : machs = va_arg (ap, unsigned int); @@ -1422,9 +1422,6 @@ xstormy16_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) machs = (1 << MAX_MACHS) - 1; /* Base mach is always selected. */ machs |= 1; - /* ISA unspecified means "all". */ - if (isas == 0) - isas = (1 << MAX_ISAS) - 1; if (endian == CGEN_ENDIAN_UNKNOWN) { /* ??? If target has only one, could have a default. */ @@ -1432,7 +1429,7 @@ xstormy16_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) abort (); } - cd->isas = isas; + cd->isas = cgen_bitset_copy (isas); cd->machs = machs; cd->endian = endian; /* FIXME: for the sparc case we can determine insn-endianness statically. diff --git a/opcodes/xstormy16-desc.h b/opcodes/xstormy16-desc.h index 823a03b..4614fa5 100644 --- a/opcodes/xstormy16-desc.h +++ b/opcodes/xstormy16-desc.h @@ -25,6 +25,8 @@ with this program; if not, write to the Free Software Foundation, Inc., #ifndef XSTORMY16_CPU_H #define XSTORMY16_CPU_H +#include "opcode/cgen-bitset.h" + #define CGEN_ARCH xstormy16 /* Given symbol S, return xstormy16_cgen_. */ @@ -184,6 +186,15 @@ typedef enum cgen_ifld_attr { /* Number of non-boolean elements in cgen_ifld_attr. */ #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) +/* cgen_ifld attribute accessor macros. */ +#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0) + /* Enum declaration for xstormy16 ifield types. */ typedef enum ifield_type { XSTORMY16_F_NIL, XSTORMY16_F_ANYOF, XSTORMY16_F_RD, XSTORMY16_F_RDM @@ -211,6 +222,13 @@ typedef enum cgen_hw_attr { /* Number of non-boolean elements in cgen_hw_attr. */ #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) +/* cgen_hw attribute accessor macros. */ +#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0) +#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0) +#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0) + /* Enum declaration for xstormy16 hardware types. */ typedef enum cgen_hw_type { HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR @@ -234,6 +252,17 @@ typedef enum cgen_operand_attr { /* Number of non-boolean elements in cgen_operand_attr. */ #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) +/* cgen_operand attribute accessor macros. */ +#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) + /* Enum declaration for xstormy16 operand types. */ typedef enum cgen_operand_type { XSTORMY16_OPERAND_PC, XSTORMY16_OPERAND_PSW_Z8, XSTORMY16_OPERAND_PSW_Z16, XSTORMY16_OPERAND_PSW_CY @@ -267,6 +296,19 @@ typedef enum cgen_insn_attr { /* Number of non-boolean elements in cgen_insn_attr. */ #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) +/* cgen_insn attribute accessor macros. */ +#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0) +#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0) +#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0) +#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0) + /* cgen.h uses things we just defined. */ #include "opcode/cgen.h" diff --git a/opcodes/xstormy16-dis.c b/opcodes/xstormy16-dis.c index 91cde6b..aaff53f 100644 --- a/opcodes/xstormy16-dis.c +++ b/opcodes/xstormy16-dis.c @@ -4,7 +4,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. - the resultant file is machine generated, cgen-dis.in isn't - Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005 + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005 Free Software Foundation, Inc. This file is part of the GNU Binutils and GDB, the GNU debugger. @@ -476,7 +476,7 @@ default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) typedef struct cpu_desc_list { struct cpu_desc_list *next; - int isa; + CGEN_BITSET *isa; int mach; int endian; CGEN_CPU_DESC cd; @@ -488,11 +488,12 @@ print_insn_xstormy16 (bfd_vma pc, disassemble_info *info) static cpu_desc_list *cd_list = 0; cpu_desc_list *cl = 0; static CGEN_CPU_DESC cd = 0; - static int prev_isa; + static CGEN_BITSET *prev_isa; static int prev_mach; static int prev_endian; int length; - int isa,mach; + CGEN_BITSET *isa; + int mach; int endian = (info->endian == BFD_ENDIAN_BIG ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE); @@ -515,25 +516,34 @@ print_insn_xstormy16 (bfd_vma pc, disassemble_info *info) #endif #ifdef CGEN_COMPUTE_ISA - isa = CGEN_COMPUTE_ISA (info); + { + static CGEN_BITSET *permanent_isa; + + if (!permanent_isa) + permanent_isa = cgen_bitset_create (MAX_ISAS); + isa = permanent_isa; + cgen_bitset_clear (isa); + cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info)); + } #else isa = info->insn_sets; #endif /* If we've switched cpu's, try to find a handle we've used before */ if (cd - && (isa != prev_isa + && (cgen_bitset_compare (isa, prev_isa) != 0 || mach != prev_mach || endian != prev_endian)) { cd = 0; for (cl = cd_list; cl; cl = cl->next) { - if (cl->isa == isa && + if (cgen_bitset_compare (cl->isa, isa) == 0 && cl->mach == mach && cl->endian == endian) { cd = cl->cd; + prev_isa = cd->isas; break; } } @@ -549,7 +559,7 @@ print_insn_xstormy16 (bfd_vma pc, disassemble_info *info) abort (); mach_name = arch_type->printable_name; - prev_isa = isa; + prev_isa = cgen_bitset_copy (isa); prev_mach = mach; prev_endian = endian; cd = xstormy16_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, @@ -562,7 +572,7 @@ print_insn_xstormy16 (bfd_vma pc, disassemble_info *info) /* Save this away for future reference. */ cl = xmalloc (sizeof (struct cpu_desc_list)); cl->cd = cd; - cl->isa = isa; + cl->isa = prev_isa; cl->mach = mach; cl->endian = endian; cl->next = cd_list; diff --git a/opcodes/xstormy16-opc.c b/opcodes/xstormy16-opc.c index 8237472..14823ee 100644 --- a/opcodes/xstormy16-opc.c +++ b/opcodes/xstormy16-opc.c @@ -1010,27 +1010,27 @@ static const CGEN_IBASE xstormy16_cgen_macro_insn_table[] = /* mov Rx,#$imm8 */ { -1, "movimm8", "mov", 16, - { 0|A(ALIAS), { (1<