From 3943c96b075b8584c9d9417c319371394b928bd6 Mon Sep 17 00:00:00 2001 From: Nick Clifton Date: Fri, 15 Sep 2000 23:55:50 +0000 Subject: Replace StrongARM property with v4 and v5 properties. --- sim/arm/ChangeLog | 24 +++++++++++++++++ sim/arm/armdefs.h | 30 +++++---------------- sim/arm/armemu.h | 32 +++++++++++++++------- sim/arm/arminit.c | 17 +++++++----- sim/arm/armrdi.c | 27 ++++++++++--------- sim/arm/wrapper.c | 79 +++++++++++++++++++++++++++++-------------------------- 6 files changed, 119 insertions(+), 90 deletions(-) diff --git a/sim/arm/ChangeLog b/sim/arm/ChangeLog index 2f1d531..b66a340 100644 --- a/sim/arm/ChangeLog +++ b/sim/arm/ChangeLog @@ -1,3 +1,27 @@ +2000-09-15 Nick Clifton + + * armdefs.h: Rename StrongARM property to v4_ARM and add v5 ARM + property. Delete unnecessary processor names. + (ARM_Strong_Prop): Delete. + (STRONGARM): Delete. + (ARM_v4_Prop): Add. + (ARM_v5_Prop): Add + (State): Delete is_StrongARM boolean. Add is_v4 and is_v5 + booleans. + + * armemu.h (BUSUSEDINCPCS): Use is_v4 boolean. + (BUSUSEDINCPCN): Use is_v4 boolean. + + * arminit.c (ARMul_NewState): Initialise is_v4 and is_v5 fields. + (ARMul_SelectProcessor): Change second parameter from 'processor' + to 'properties'. Set is_v4 and is_v5 booleans in State. + + * armrdi.c: Remove use of ARM processor names. Replace with ARM + processor properties. + + * wrapper.c (sim_create_inferior): Choose properties passed to + ARMul_SelectProcessor based on machine number. + 2000-08-14 Nick Clifton * armemu.c (LHPOSTDOWN): Compute write back value before diff --git a/sim/arm/armdefs.h b/sim/arm/armdefs.h index 72dae0a..61ab9c5 100644 --- a/sim/arm/armdefs.h +++ b/sim/arm/armdefs.h @@ -123,9 +123,9 @@ struct ARMul_State const struct Dbg_HostosInterface *hostif; - unsigned is_StrongARM; /* Are we emulating a StrongARM? */ - - int verbose; /* non-zero means print various messages like the banner */ + unsigned is_v4; /* Are we emulating a v4 architecture (or higher) ? */ + unsigned is_v5; /* Are we emulating a v5 architecture ? */ + unsigned verbose; /* Print various messages like the banner */ }; #define ResetPin NresetSig @@ -139,7 +139,7 @@ struct ARMul_State #define LateAbortPin lateabtSig /***************************************************************************\ -* Types of ARM we know about * +* Properties of ARM we know about * \***************************************************************************/ /* The bitflags */ @@ -148,26 +148,8 @@ struct ARMul_State #define ARM_Debug_Prop 0x10 #define ARM_Isync_Prop ARM_Debug_Prop #define ARM_Lock_Prop 0x20 -#define ARM_Strong_Prop 0x40 - -/* ARM2 family */ -#define ARM2 (ARM_Fix26_Prop) -#define ARM2as ARM2 -#define ARM61 ARM2 -#define ARM3 ARM2 - -#ifdef ARM60 /* previous definition in armopts.h */ -#undef ARM60 -#endif - -/* ARM6 family */ -#define ARM6 (ARM_Lock_Prop) -#define ARM60 ARM6 -#define ARM600 ARM6 -#define ARM610 ARM6 -#define ARM620 ARM6 - -#define STRONGARM (ARM_Strong_Prop) +#define ARM_v4_Prop 0x40 +#define ARM_v5_Prop 0x80 /***************************************************************************\ * Macros to extract instruction fields * diff --git a/sim/arm/armemu.h b/sim/arm/armemu.h index 7bca8d3..81ecd52 100644 --- a/sim/arm/armemu.h +++ b/sim/arm/armemu.h @@ -230,15 +230,29 @@ extern ARMword isize; #define RESUME 8 #define NORMALCYCLE state->NextInstr = 0 -#define BUSUSEDN state->NextInstr |= 1 /* the next fetch will be an N cycle */ -#define BUSUSEDINCPCS do { if (! state->is_StrongARM) { \ - state->Reg[15] += isize ; /* a standard PC inc and an S cycle */ \ - state->NextInstr = (state->NextInstr & 0xff) | 2; \ - } } while (0) -#define BUSUSEDINCPCN do { if (state->is_StrongARM) BUSUSEDN; else { \ - state->Reg[15] += isize ; /* a standard PC inc and an N cycle */ \ - state->NextInstr |= 3; \ - } } while (0) +#define BUSUSEDN state->NextInstr |= 1 /* The next fetch will be an N cycle. */ +#define BUSUSEDINCPCS \ + do \ + { \ + if (! state->is_v4) \ + { \ + state->Reg[15] += isize ; /* A standard PC inc and an S cycle. */ \ + state->NextInstr = (state->NextInstr & 0xff) | 2; \ + } \ + } \ + while (0) +#define BUSUSEDINCPCN \ + do \ + { \ + if (state->is_v4) \ + BUSUSEDN; \ + else \ + { \ + state->Reg[15] += isize ; /* A standard PC inc and an N cycle. */ \ + state->NextInstr |= 3; \ + } \ + } \ + while (0) #define INCPC state->Reg[15] += isize ; /* a standard PC inc */ \ state->NextInstr |= 2 #define FLUSHPIPE state->NextInstr |= PRIMEPIPE diff --git a/sim/arm/arminit.c b/sim/arm/arminit.c index 3ee4c69..a3f0001 100644 --- a/sim/arm/arminit.c +++ b/sim/arm/arminit.c @@ -85,7 +85,7 @@ ARMul_NewState (void) } for (i = 0; i < 7; i++) state->Spsr[i] = 0; - + state->Mode = USER26MODE; state->CallDebug = FALSE; @@ -124,20 +124,22 @@ ARMul_NewState (void) state->lateabtSig = LOW; state->bigendSig = LOW; - state->is_StrongARM = LOW; + state->is_v4 = LOW; + state->is_v5 = LOW; ARMul_Reset (state); - return (state); + + return state; } /***************************************************************************\ -* Call this routine to set ARMulator to model a certain processor * + Call this routine to set ARMulator to model certain processor properities \***************************************************************************/ void -ARMul_SelectProcessor (ARMul_State * state, unsigned processor) +ARMul_SelectProcessor (ARMul_State * state, unsigned properties) { - if (processor & ARM_Fix26_Prop) + if (properties & ARM_Fix26_Prop) { state->prog32Sig = LOW; state->data32Sig = LOW; @@ -150,7 +152,8 @@ ARMul_SelectProcessor (ARMul_State * state, unsigned processor) state->lateabtSig = LOW; - state->is_StrongARM = (processor & ARM_Strong_Prop) ? HIGH : LOW; + state->is_v4 = (properties & (ARM_v4_Prop | ARM_v5_Prop)) ? HIGH : LOW; + state->is_v5 = (properties & ARM_v5_Prop) ? HIGH : LOW; } /***************************************************************************\ diff --git a/sim/arm/armrdi.c b/sim/arm/armrdi.c index a42b310..14904e3 100644 --- a/sim/arm/armrdi.c +++ b/sim/arm/armrdi.c @@ -180,22 +180,23 @@ RDIInit (unsigned type) typedef struct { char name[16]; - unsigned val; + unsigned properties; } Processor; -Processor const p_arm2 = { "ARM2", ARM2 }; -Processor const p_arm2as = { "ARM2AS", ARM2as }; -Processor const p_arm61 = { "ARM61", ARM61 }; -Processor const p_arm3 = { "ARM3", ARM3 }; -Processor const p_arm6 = { "ARM6", ARM6 }; -Processor const p_arm60 = { "ARM60", ARM60 }; -Processor const p_arm600 = { "ARM600", ARM600 }; -Processor const p_arm610 = { "ARM610", ARM610 }; -Processor const p_arm620 = { "ARM620", ARM620 }; -Processor const p_unknown = { "", UNKNOWNPROC }; - -Processor const *const processors[] = { +Processor const p_arm2 = { "ARM2", ARM_Fix26_Prop }; +Processor const p_arm2as = { "ARM2AS", ARM_Fix26_Prop }; +Processor const p_arm61 = { "ARM61", ARM_Fix26_Prop }; +Processor const p_arm3 = { "ARM3", ARM_Fix26_Prop }; +Processor const p_arm6 = { "ARM6", ARM_Lock_Prop }; +Processor const p_arm60 = { "ARM60", ARM_Lock_Prop }; +Processor const p_arm600 = { "ARM600", ARM_Lock_Prop }; +Processor const p_arm610 = { "ARM610", ARM_Lock_Prop }; +Processor const p_arm620 = { "ARM620", ARM_Lock_Prop }; +Processor const p_unknown = { "", 0 }; + +Processor const *const processors[] = +{ &p_arm6, /* default: must come first */ &p_arm2, &p_arm2as, diff --git a/sim/arm/wrapper.c b/sim/arm/wrapper.c index b7b7a62..b5ecd31 100644 --- a/sim/arm/wrapper.c +++ b/sim/arm/wrapper.c @@ -122,11 +122,12 @@ sim_write (sd, addr, buffer, size) int size; { int i; + init (); + for (i = 0; i < size; i++) - { - ARMul_WriteByte (state, addr + i, buffer[i]); - } + ARMul_WriteByte (state, addr + i, buffer[i]); + return size; } @@ -208,40 +209,44 @@ sim_create_inferior (sd, abfd, argv, env) mach = bfd_get_mach (abfd); - switch (mach) { - default: - (*sim_callback->printf_filtered) (sim_callback, - "Unknown machine type; please update sim_create_inferior.\n"); - /* fall through */ - - case 0: /* arm */ - /* We wouldn't set the machine type with earlier toolchains, so we - explicitly select a processor capable of supporting all ARM - 32bit mode. */ - /* fall through */ - - case 5: /* armv4 */ - case 6: /* armv4t */ - case 7: /* armv5 */ - case 8: /* armv5t */ - ARMul_SelectProcessor (state, STRONGARM); - /* Reset mode to ARM. A gdb user may rerun a program that had entered - THUMB mode from the start and cause the ARM-mode startup code to be - executed in THUMB mode. */ - ARMul_SetCPSR (state, USER32MODE); - break; - - case 3: /* armv3 */ - case 4: /* armv3m */ - ARMul_SelectProcessor (state, ARM600); - break; - - case 1: /* armv2 */ - case 2: /* armv2a */ - ARMul_SelectProcessor (state, ARM2); - break; - } - + switch (mach) + { + default: + (*sim_callback->printf_filtered) (sim_callback, + "Unknown machine type; please update sim_create_inferior.\n"); + /* fall through */ + + case 0: /* arm */ + /* We wouldn't set the machine type with earlier toolchains, so we + explicitly select a processor capable of supporting all ARM + 32bit mode. */ + /* fall through */ + + case 5: /* armv4 */ + case 6: /* armv4t */ + case 7: /* armv5 */ + case 8: /* armv5t */ + if (mach == 7 || mach == 8) + ARMul_SelectProcessor (state, ARM_v5_Prop); + else + ARMul_SelectProcessor (state, ARM_v4_Prop); + /* Reset mode to ARM. A gdb user may rerun a program that had entered + THUMB mode from the start and cause the ARM-mode startup code to be + executed in THUMB mode. */ + ARMul_SetCPSR (state, USER32MODE); + break; + + case 3: /* armv3 */ + case 4: /* armv3m */ + ARMul_SelectProcessor (state, ARM_Lock_Prop); + break; + + case 1: /* armv2 */ + case 2: /* armv2a */ + ARMul_SelectProcessor (state, ARM_Fix26_Prop); + break; + } + if (argv != NULL) { /* -- cgit v1.1