aboutsummaryrefslogtreecommitdiff
path: root/sim
AgeCommit message (Expand)AuthorFilesLines
2022-01-06sim: ppc: migrate to standard uintXX_t typesMike Frysinger37-1343/+1332
2022-01-06sim: common: migrate to standard uintXX_t typesMike Frysinger22-432/+425
2022-01-06sim: igen: migrate to standard uintXX_t typesMike Frysinger6-27/+9
2022-01-06sim: mips: migrate to standard uintXX_t typesMike Frysinger17-1083/+1083
2022-01-06sim: cris: migrate to standard uintXX_t typesMike Frysinger7-80/+80
2022-01-06sim: iq2000: migrate to standard uintXX_t typesMike Frysinger1-4/+4
2022-01-06sim: synacor: migrate to standard uintXX_t typesMike Frysinger2-27/+27
2022-01-06sim: msp430: migrate to standard uintXX_t typesMike Frysinger2-15/+15
2022-01-06sim: riscv: migrate to standard uintXX_t typesMike Frysinger1-28/+28
2022-01-06sim: bfin: migrate to standard uintXX_t typesMike Frysinger1-2/+2
2022-01-06sim: testsuite: migrate to standard uintXX_t typesMike Frysinger4-19/+19
2022-01-06sim: erc32: migrate to standard uintXX_t typesMike Frysinger7-312/+305
2022-01-06sim: mn10300: migrate to standard uintXX_t typesMike Frysinger11-505/+498
2022-01-06sim: v850: migrate to standard uintXX_t typesMike Frysinger5-111/+105
2022-01-06sim: m68hc11: migrate to standard uintXX_t typesMike Frysinger13-273/+265
2022-01-06sim: d10v: migrate to standard uintXX_t typesMike Frysinger4-273/+265
2022-01-06sim: cr16: migrate to standard uintXX_t typesMike Frysinger3-630/+621
2022-01-01sim: ppc: drop natural typesMike Frysinger4-31/+10
2022-01-01sim: mips: clean up bad style/whitespaceMike Frysinger23-345/+345
2022-01-01sim: tweak copyright lines for gnulib update-copyrightMike Frysinger23-23/+23
2022-01-01Automatic Copyright Year update after running gdb/copyright.pyJoel Brobecker670-670/+670
2021-12-16sim: mips/or1k: drop redundant arg to bitsize macroMike Frysinger4-6/+4
2021-12-16sim: fix mingw builds with replacement gnulib openMike Frysinger1-2/+2
2021-12-09sim: use ## for automake commentsMike Frysinger25-882/+419
2021-12-04sim: include ansidecl.h when neededMike Frysinger16-1/+26
2021-12-04sim: include stdint.h when neededMike Frysinger3-0/+3
2021-12-04sim: include stdarg.h when usedMike Frysinger20-0/+22
2021-12-04sim: reorder header includesMike Frysinger44-162/+173
2021-12-04sim: moxie: hoist dtb rules up to common buildsMike Frysinger4-49/+116
2021-12-04sim: m68hc11: delete unused profile flagsMike Frysinger1-1/+0
2021-12-04sim: msp430: delete redundant comments & settingsMike Frysinger1-22/+0
2021-12-04sim: erc32: drop old configure targetMike Frysinger1-8/+0
2021-12-04sim: m32c/rl78: drop redundant -Wall settingsMike Frysinger2-3/+1
2021-12-04sim: frv: split up testsuite a bitMike Frysinger9-19/+136
2021-11-28sim: testsuite: drop most specific istarget checksMike Frysinger42-47/+42
2021-11-28sim: testsuite: support parallel executionMike Frysinger2-10/+80
2021-11-28sim: testsuite: expand arch specific toolchain settingsMike Frysinger3-7/+63
2021-11-28sim: testsuite: setup per-port toolchain settings for multitarget buildMike Frysinger5-3/+895
2021-11-28sim: add checks to core headers to prevent incorrect common buildingMike Frysinger3-2/+8
2021-11-28sim: unify syscall.o buildingMike Frysinger3-1/+22
2021-11-28sim: drop unused gentmap & nltvals.def logicMike Frysinger6-422/+31
2021-11-28sim: mcore: switch to new target-newlib-syscallMike Frysinger2-3/+5
2021-11-28sim: riscv: switch to new target-newlib-syscallMike Frysinger2-3/+2
2021-11-28sim: cr16: switch to new target-newlib-syscallMike Frysinger3-51/+28
2021-11-28sim: d10v: switch to new target-newlib-syscallMike Frysinger3-36/+26
2021-11-28sim: sh: switch to new target-newlib-syscallMike Frysinger2-25/+23
2021-11-28sim: v850: switch to new target-newlib-syscallMike Frysinger3-67/+26
2021-11-28sim: iq2000/lm32/m32c/moxie/rx: switch to new target-newlib-syscall.hMike Frysinger5-35/+35
2021-11-28sim: nltvals: pull target syscalls out into a dedicated source fileMike Frysinger9-65/+987
2021-11-28sim: frv: resolve syscalls dynamicallyMike Frysinger1-2/+1
generated by cgit v1.1 at 2024-07-20 07:39:22 +0000