aboutsummaryrefslogtreecommitdiff
path: root/sim
AgeCommit message (Collapse)AuthorFilesLines
2003-09-192003-09-19 Michael Snyder <msnyder@redhat.com>Michael Snyder2-64/+5
* sim/frv/nldqi.cgs: Remove. This insn was never implemented by Fujitsu.
2003-09-192003-09-19 Dave Brolley <brolley@redhat.com>Dave Brolley3-2/+8
* sim/frv/rstqf.cgs: Use nldq instead of nldqi. * sim/frv/rstq.cgs: Use nldq instead of nldqi.
2003-09-12Correct last entry.Dave Brolley1-2/+1
2003-09-122003-09-12 Dave Brolley <brolley@redhat.com>Dave Brolley11-77/+302
* registers.c (frv_check_spr_read_access): Check for access to ACC4-ACC63 and ACCG4-ACCG63. * profile.h (frv-desc.h): #include it. (spr_busy): New member of FRV_PROFILE_STATE. (spr_latency): Ditto. (GNER_FOR_GR): New macro. (FNER_FOR_FR): New maccro. (update_SPR_latency): New function. (vliw_wait_for_SPR): New function. * profile.c (profile-fr550.h): #include it. (update_latencies): Update SPR latencies. (update_target_latencies): Ditto. (update_SPR_latency): New function. (vliw_wait_for_SPR): New function. * profile-fr500.c (frvbf_model_fr500_u_idiv): Record GNER latency. (frvbf_model_fr500_u_trap): Removed unused variable, ps. (frvbf_model_fr500_u_check): Ditto. (frvbf_model_fr500_u_clrgr): New unit modeller for fr500. (frvbf_model_fr500_u_clrfr): Ditto. (frvbf_model_fr500_u_spr2gr): Wait for SPR. (frvbf_model_fr500_u_gr2spr): Ditto. * frv-sim.h (H_SPR_ACC4): New macro. (H_SPR_ACCG4): New macro; (H_SPR_ACC0): Removed. (H_SPR_ACCG0): Removed. * arch.h,model.c,sem[ch],decode.[ch]: Regenerated.
2003-09-112003-09-11 Michael Snyder <msnyder@redhat.com>Michael Snyder2-1/+6
* sim/testsuite/sim/frv/movgs.cgs: Change lcr to spr[273], which according to the comments seems to be the intent.
2003-09-102003-09-10 Dave Brolley <brolley@redhat.com>Dave Brolley2-9/+21
* profile.c (slot_names): FM1 was listed twice. Changed first instance to FM0. Added IALL, FMALL and FMLOW. (print_parallel): Don't examine slots with no insns.
2003-09-092003-09-09 Dave Brolley <brolley@redhat.com>Dave Brolley5-7/+13
* sim/frv/maddaccs.cgs: move to fr400 subdirectory. * sim/frv/msubaccs.cgs: move to fr400 subdirectory. * sim/frv/masaccs.cgs: move to fr400 subdirectory.
2003-09-092003-09-09 Dave Brolley <brolley@redhat.com>Dave Brolley2-3/+13
* frv.c (do_media_average): Select machine using a switch.
2003-09-082003-09-08 Dave Brolley <brolley@redhat.com>Dave Brolley2-1/+11
On behalf of Doug Evans <dje@sebabeach.org> * Makefile.in (stamp-arch,stamp-cpu,stamp-xcpu): Pass archfile to cgen.
2003-09-082003-09-08 Dave Brolley <brolley@redhat.com>Dave Brolley2-2/+12
On behalf of Doug Evans <dje@sebabeach.org> * Makefile.in (stamp-arch,stamp-cpu, stamp-desc): Pass archfile to cgen.
2003-09-082003-09-08 Dave Brolley <brolley@redhat.com>Dave Brolley2-6/+8
On behalf of Doug Evans <dje@sebabeach.org> * Makefile.in (stamp-arch,stamp-cpu): Pass archfile to cgen. Remove copying of .cpu file to cgen/cpu, no longer needed.
2003-09-082003-09-08 Dave Brolley <brolley@redhat.com>Dave Brolley3-11/+25
On behalf of Doug Evans <dje@sebabeach.org> * cgen.sh: New arg archfile. * Make-common.in (cgen-arch,cgen-cpu,cgen-defs,cgen-decode, cgen-cpu-decode,cgen-desc): Update call to cgen.sh.
2003-09-05Add support for v850e1 instructionsNick Clifton4-0/+76
2003-09-03003-09-03 Dave Brolley <brolley@redhat.com>Dave Brolley6-38/+354
* cpu.h, model.c, sem.c, decode.h, decode.c: Regenerated.
2003-09-03Spelling fix by the ChangeLog police.Ben Elliston1-2/+2
2003-09-032003-09-03 Michael Snyder <msnyder@redhat.com>Michael Snyder2-1/+6
* sim/frv/fr500/mclracc.cgs: Change mach to 'all', to be consistant with other tests in the directory.
2003-09-032003-09-03 Michael Snyder <msnyder@redhat.com>Michael Snyder3-4/+45
* sim/frv/interrupts/Ipipe-fr400.cgs: New file. * sim/frv/interrupts/Ipipe-fr500.cgs: New file. * sim/frv/interrupts/Ipipe.cgs: Remove (replaced by above).
2003-09-03 * Makefile.in (FLAGS_TO_PASS): Pass down $(bindir) and $(mandir).Andreas Schwab2-0/+6
2003-08-292003-08-29 Dave Brolley <brolley@redhat.com>Dave Brolley1-0/+6
* Makefile.in (stamp-arch): Copy frv.cpu from $(srcdir)../../cpu temporarily when regenerating files. (stamp-cpu): Ditto.
2003-08-292003-08-29 Dave Brolley <brolley@redhat.com>Dave Brolley2-3/+6
* MAINTAINERS: Add myself as maintainer of the FRV port.
2003-08-292003-08-20 Michael Snyder <msnyder@redhat.com>Dave Brolley3-0/+15
Dave Brolley <brolley@redhat.com> * frv/: New directory, simulator for the Fujitsu FR-V. * testsuite/frv-elf/: New directory. * testsuite/sim/frv/: New directory. * configure.in: Add frv configury. * configure: Regenerate.
2003-08-292003-08-20 Michael Snyder <msnyder@redhat.com>Dave Brolley4-0/+45
Dave Brolley <brolley@redhat.com> * cgen-par.h (flags, word1): New target-specific fields of CGEN_WRITE_QUEUE_ELEMENT. (CGEN_WRITE_QUEUE_ELEMENT_FLAGS): New accessor macro. (CGEN_WRITE_QUEUE_ELEMENT_WORD1): New accessor macro. * gennltvals.sh: Add frv target. * nltvals.def: Add frv target.
2003-08-292003-08-20 Michael Snyder <msnyder@redhat.com>Dave Brolley1-0/+6
On behalf of Dave Brolley * sim/frv: New testsuite. * frv-elf: New testsuite.
2003-08-29New sim testsuite for Fujitsu FRV. Contributed by Red Hat.Dave Brolley794-0/+113410
2003-08-29New simulator for Fujitsu frv contributed by Red Hat.Dave Brolley39-0/+145235
2003-08-28Index: common/ChangeLogAndrew Cagney6-11/+30
2003-08-28 Andrew Cagney <cagney@redhat.com> * dv-glue.c (hw_glue_finish): Change %d to %ld to match sizeof. * sim-options.c (print_help): Cast the format with specifier to "int". Index: mn10300/ChangeLog 2003-08-28 Andrew Cagney <cagney@redhat.com> * dv-mn103ser.c (do_polling_event): Change type of "serial_reg" to "long". (read_status_reg): Cast "serial_reg" to "long". * dv-mn103tim.c (do_counter_event): Change type of "timer_nr" to "long". (do_counter6_event, write_mode_reg, write_tm6md): Ditto.
2003-08-112003-08-11 Michael Snyder <msnyder@redhat.com>Michael Snyder4-0/+118
* macl.s: New file. * macw.s: New file. * allinsn.exp: Add new tests for mac.w and mac.l.
2003-08-112003-08-11 Shrinivas Atre <shrinivasa@KPITCummins.com>Michael Snyder3-3/+60
* sim/sh/gencode.c ( tab[] ): Addition of MAC.L handler and correction for MAC.W handler * sim/sh/interp.c ( macl ): New Function. Implementation of MAC.L handler.
2003-08-10 * MAINTAINERS: Update my mail address.Ben Elliston2-1/+5
2003-08-092003-08-09 Andrew Cagney <cagney@redhat.com>Andrew Cagney2-2/+14
* MAINTAINERS: Andrew Cagney (mips) and Geoff Keating (ppc) drop maintenance. List igen and sh maintainers. Mention that target and global maintainers pick up the slack.
2003-08-08 * dv-m68hc11tim.c (cycle_to_string): Add flags parameter to betterStephane Carrez8-65/+170
control the translation. (m68hc11tim_print_timer): Update cycle_to_string conversion. (m68hc11tim_timer_event): Fix handling of output compare register with its interrupts. (m68hc11tim_io_write_buffer): Check output compare after setting M6811_TMSK1. (m68hc11tim_io_read_buffer): Fix compilation warning. * dv-m68hc11.c (m68hc11_option_handler): Likewise. * dv-m68hc11spi.c (m68hc11spi_info): Likewise. * dv-m68hc11sio.c (m68hc11sio_info): Likewise. * interrupts.c (interrupts_info): Likewise. (interrupts_reset): Recognize bootstrap mode. * sim-main.h (PRINT_CYCLE, PRINT_TIME): New defines. (_sim_cpu): Add cpu_start_mode. (cycle_to_string): Add flags member. * m68hc11_sim.c (OPTION_CPU_BOOTSTRAP): New option. (cpu_options): Declare new option bootstrap. (cpu_option_handler): Handle it. (cpu_info): Update call to cycle_to_string.
2003-08-08 * sim-main.h (phys_to_virt): Use memory bank parameters to translateStephane Carrez5-25/+137
the physical address in virtual address. (struct _sim_cpu): Add memory bank members. * m68hc11_sim.c (cpu_initialize): Clear memory bank parameters. * interp.c (sim_hw_configure): Create memory bank according to memory bank parameters. (sim_get_bank_parameters): New function to obtain memory bank config from the symbol table. (sim_prepare_for_program): Call it to obtain the memory bank parameters. (sim_open): Call sim_prepare_for_program. * dv-m68hc11.c (m68hc11cpu_io_write_buffer): Use memory bank parameters to check if address is within bank window. (m68hc11cpu_io_read_buffer): Likewise. (attach_m68hc11_regs): Map the memory bank according to memory bank parameters.
2003-08-08 * sim-main.h (PAGE_REGNUM, Z_REGNUM): Use same numbering as gdb.Stephane Carrez2-2/+6
2003-08-08 * m68hc11_sim.c (print_io_word): New function to print 16-bit value.Stephane Carrez4-4/+99
* sim-main.h (print_io_word): Declare. * dv-m68hc11tim.c (tmsk1_desc): New description table for TMSK1. (tflg1_desc): Likewise for TFLG1. (m68hc11tim_info): Print input and output compare registers
2003-08-072003-08-07 Michael Snyder <msnyder@redhat.com>Michael Snyder2-1/+5
* gencode.c (expand_ppi_code): Comment spelling fix.
2003-07-292003-07-22 Michael Snyder <msnyder@redhat.com>Michael Snyder5-1/+787
* cmpw.s: Add test for less-than-zero immediate. * shll.s: Test for shll reg, reg. * shlr.s: Test for shlr reg, reg. * mova.s: Add dozens of new mova tests.
2003-07-292003-07-18 Michael Snyder <msnyder@redhat.com>Michael Snyder2-36/+109
* compile.c (decode): Enhancements for mova. Initialize cst, reg, and rdisp inside the loop, for each new instruction. Defer correction of the disp2 values until later, and then adjust them by the size of the first operand, rather than the size of the instruction. (sim_resume): For mova, adjust the size of the second operand according to the type of the first operand (INDEXB vs. INDEXW). In cases where there is only one operand, the other two must both be composed on the fly.
2003-07-262003-07-25 Michael Snyder <msnyder@redhat.com>Michael Snyder12-0/+1346
* pshai.s, pshar.s, pshli.s, pshlr.s: New files. * allinsn.exp: Add psha, pshl tests. * pdec.s, pinc.s, padd.s, paddc.s: New files. * allinsn.exp: Add pdec, pinc, padd, paddc tests. * pand.s, pdmsb.s: New files. * allinsn.exp: Add pand, pdmsb tests.
2003-07-262003-07-08 Michael Snyder <msnyder@redhat.com>Michael Snyder7-0/+856
* allinsn.exp, testutils.inc, add.s, fabs.s, fadd.s, fcmpeq.s, fcmpgt.s, fcnvds.s, fcnvsd.s, fdiv.s, fldi0.s, fldi1.s, flds.s, float.s, fmac.s, fmov.s, fmul.s, fneg.s, frchg.s, fschg.s, fsqrt.s, fsub.s, ftrc.s, shll16.s, shll2.s, shll8.s, shll.s, shlr16.s, shlr2.s, shlr8.s, shlr.s, swap.s: New files.
2003-07-252003-07-25 Michael Snyder <msnyder@redhat.com>Michael Snyder2-6/+12
* gencode.c (pshl): Change < to <= (shift by 16 is allowed). Cast argument of >> to unsigned to prevent sign extension. (psha): Change < to <= (shift by 32 is allowed).
2003-07-252003-07-24 Michael Snyder <msnyder@redhat.com>Michael Snyder2-1/+5
* gencode.c: Fix typo in comment.
2003-07-242003-07-23 Michael Snyder <msnyder@redhat.com>Michael Snyder2-17/+28
* gencode.c: A few more fix-ups of refs and defs. (frchg): Raise SIGILL if in double-precision mode. (ldtlb): We don't simulate cache, so this is a no-op. (movsxy_tab): Correct a few bit pattern errors.
2003-07-232003-07-09 Michael Snyder <msnyder@redhat.com>Michael Snyder2-2/+3
* gencode.c (prnd): Clear LSW of result to zeros.
2003-07-232003-07-23 Michael Snyder <msnyder@redhat.com>Michael Snyder2-0/+37
* pmuls.s: New file.
2003-07-232003-07-09 Michael Snyder <msnyder@redhat.com>Michael Snyder2-3/+4
* gencode.c (pmuls): Expression is mis-parenthesized.
2003-07-232003-07-09 Michael Snyder <msnyder@redhat.com>Michael Snyder3-4/+15
* configure.in: Add testsuite to extra_subdirs for sh. * configure: Regenerate.
2003-07-232003-07-09 Michael Snyder <msnyder@redhat.com>Michael Snyder1-0/+4
* sim/sh: New directory. Tests for Renesas sh family.
2003-07-232003-07-08 Michael Snyder <msnyder@redhat.com>Michael Snyder26-0/+2293
* allinsn.exp, testutils.inc, add.s, fabs.s, fadd.s, fcmpeq.s, fcmpgt.s, fcnvds.s, fcnvsd.s, fdiv.s, fldi0.s, fldi1.s, flds.s, float.s, fmac.s, fmov.s, fmul.s, fneg.s, frchg.s, fschg.s, fsqrt.s, fsub.s, ftrc.s, shll16.s, shll2.s, shll8.s, shll.s, shlr16.s, shlr2.s, shlr8.s, shlr.s, swap.s: New files.
2003-07-232003-07-09 Michael Snyder <msnyder@redhat.com>Michael Snyder2-1/+8
* gencode.c (ppi_gensim): For a conditional ppi insn, if the condition is false, we want to return (not break). A break will take us to the end of the function where registers will be updated, whereas the desired outcome is for nothing to change.
2003-07-232003-06-27 Michael Snyder <msnyder@redhat.com>Michael Snyder2-25/+38
* gencode.c (op tab): Some fix-ups of refs and defs. (ocbi, ocbp): Cache not simulated, but may cause memory fault. (gensym_caselist): Add default case to switch statement. (expand_ppi_code): Add default case to switch statement.
generated by cgit v1.1 at 2024-10-17 14:32:23 +0000