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The cgen code declares some macros/funcs using the trace_xxx prefix, but
the code isn't generic and only works with cgen targets. This is blocking
the creation of new common trace functions.
Let's blindly add cgen_xxx prefixes to all these symbols. Some already
use this convention to avoid conflicts, so it makes sense to align them.
In the future we might want to move some to the common trace core, but
one thing at a time.
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These macros were copied from the Blackfin port but never used, so delete
them as part of the trace unification work.
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First we convert the ETRACE_P to STRACE_EVENTS_P. This means we move from
using the sim_events.trace storage to the common sim_state_base.trace_data
array. With that deleted, the common trace init code can be simplified so
the sim state works the same as the sim cpu.
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These are the parallel to the TRACE_xxx_P macros and fill out the full
set to match the existing debug one.
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No point in duplicating the shift logic when we have macros already to
keep that all unified.
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This way we can use the IDX macros everywhere and not worry about the
encoding of the WITH_TRACE define in multiple places.
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This is the only sim that sets up its own WITH_TRACE mask and it conflicts
with the user setting their own list at configure time. Drop it to match
all the other sims.
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The interrupts.c file has a static/fuller definition that is used,
so drop this copy in interp.c.
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This code already matched the common sim reusme logic, so we can simply
drop it and pull in the common code.
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Only one place used get_word/put_word, so inline the usage there.
All the rest is dead code so trim it.
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The syscall path was the only code checking the custom exception state
after recent cleanups. Once we change that to the common engine halt
function, we can delete that state entirely.
This also helps highlight some other dead code that we can cull.
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No point in open coding this logic here when we have common size types
already that give the right answer.
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The sim-inline.h header already takes care of this for us, so punt
the local definitions.
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This allows us to use the common code for all exception handling.
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sim/common/ChangeLog:
* sim-events.c (sim_events_schedule_after_signal): Fix spelling
mistake in call to sim_engine_abort.
(sim_events_schedule_after_signal): Likewise.
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Permission was granted by Jiri Gaisler, who has a copyright assignment
on file for GDB.
sim/erc32/ChangeLog:
* configure.ac: Add copyright header.
* erc32.c: Change copyright holder to FSF. Reformat.
* exec.c, float.c, func.c, interf.c, sis.c, sis.h: Likewise.
* help.c, startsim: Add copyright header.
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[gas]
* config/rl78-defs.h (rl78_isa_g10): New.
(rl78_isa_g13): New.
(rl78_isa_g14): New.
* config/rl78-parse.y (ISA_G10): New.
(ISA_G13): New.
(ISA_G14): New.
(MULHU, MULH, MULU, DIVHU, DIVWU, MACHU, MACH): Use them.
* config/tc-rl78.c (rl78_isa_g10): New.
(rl78_isa_g13): New.
(rl78_isa_g14): New.
[gdb]
* rl78-tdep.c (rl78_analyze_prologue): Pass RL78_ISA_DEFAULT to
rl78_decode_opcode
[include]
* dis-asm.h (print_insn_rl78_g10): New.
(print_insn_rl78_g13): New.
(print_insn_rl78_g14): New.
(rl78_get_disassembler): New.
* opcode/rl78.h (RL78_Dis_Isa): New.
(rl78_decode_opcode): Add ISA parameter.
[opcodes]
* disassemble.c (disassembler): Choose suitable disassembler based
on E_ABI.
* rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
it to decode mul/div insns.
* rl78-decode.c: Regenerate.
* rl78-dis.c (print_insn_rl78): Rename to...
(print_insn_rl78_common): ...this, take ISA parameter.
(print_insn_rl78): New.
(print_insn_rl78_g10): New.
(print_insn_rl78_g13): New.
(print_insn_rl78_g14): New.
(rl78_get_disassembler): New.
[sim]
* rl78/cpu.c (g14_multiply): New.
* rl78/cpu.h (g14_multiply): New.
* rl78/load.c (rl78_load): Decode ISA completely.
* rl78/main.c (main): Expand -M to include other ISAs.
* rl78/rl78.c (decode_opcode): Decode based on ISA.
* rl78/trace.c (rl78_disasm_fn): New.
(sim_disasm_init): Reset it.
(sim_disasm_one): Get correct disassembler for ISA.
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analysis tool.
erc32 PR 18273
* sis.c (main): Remove unreachable code.
m68hc11 * gencode.c (gen_fetch_operands): Remove unreachable code.
ppc * hw_htab.c (htab_map_binary): Fix overlap check.
common * sim-fpu.c (INLINE_SIM_FPU): Fix static analysis warning by
increasing parenthesis around casts to signed values.
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This patch does whatever was done in
https://sourceware.org/ml/gdb-patches/2015-04/msg00437.html to fix
broken gdb build for the AVR target.
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bfin PR 18273
* bfin-sim.c (decode_dsp32alu_0): Remove spurious check for
s == 1.
erc32 PR 18273
* exec.c (add32): Fix typo in check for overflow.
igen PR 18273
* misc.c (a2i): Fix typos checking for uppercase letters.
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PR sim/18273
* reg.c (put_reg): Fix check for valid register number.
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These printf statements are showing "word" objects which are typedefed
from long, so make sure to use l with %x when printing them to avoid
warnings from gcc.
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Re-use the existing memory core that handles reads/writes.
The verbose command is converted to the common --verbose flag
since only a few call sites use it now.
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In preparation for converting to the common memory framework, the custom
commands get in our way. But when we realize that gdb support has been
dropped for mcore, it makes things a bit easier: the main runner does not
let you run arbitrary commands once simulation starts.
So lets disable watchpoint support until it can be converted to the common
watchpoint logic. There's already an ifdef to let us do that.
We straight up drop support for the dumpmem command (no other sim supports
this, and if it's a feature people want, we can add a common func) and the
clearstats command (not a big deal -- just restart your simulation).
We leave in place the verbose check points as a follow up commit will cut
that over to common logic.
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Now that libgloss has a header tracking the syscalls for this arch, we
can update the database to include it for the symbolic constants/maps.
Then we can switch the mcore syscall callbacks over to the common ones.
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Since newlib no longer shares the same repo as binutils/gdb, we have to go
searching further afield to locate the sources. We still look at the top
level for newlib, but if that is not found, we also try up one dir outside
of this source tree. It sucks, but better than the status quo (no workie).
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Change data ordering in emulated memory from target order (big endian)
to host order. Improves performance and simplifies most memory
operations. Requires some byte twisting during stores on little
endian hosts (intel). Also removed support for little-endian binaries.
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Now that we've unified sim-cpu, we can delete the duplicate sim-engine
hooks -- these targets defined these only because they didn't fully
implement the sim-cpu callbacks.
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This doesn't appear to have been used since 1998, but wasn't cleaned
up since. So much for being "quick" ;).
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Since every target typedefs this the same way, move it to the common code.
We have to leave Blackfin behind here for now because of inter-dependencies
on types and headers: sim-base.h includes sim-model.h which needs types in
machs.h which needs types in bfim-sim.h which needs SIM_CPU.
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Almost every target defines sim_cia the same way -- either using the
address_word type directly, or a type of equivalent size. The only
odd one out is sh64 (who has 32bit address_word and 64bit cia), and
even that case doesn't seem to make sense. We'll put off clean up
though of sh64 and at least set up a sensible default for everyone.
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Re-use the existing memory core that handles reads/writes.
This drops support for the dumpmem command, but gdb itself has
support for dumping memory regions.
The verbose command is converted to the common --verbose flag
since only two call sites use it now.
Support for the clearstats command is dropped entirely, but no
other sim really does this, and the same thing can be done by
reloading. If it's important (clearing cycle stats) to someone,
we can add a common function for it.
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The CIA_{GET,SET} macros serve the same function as CPU_PC_{GET,SET}
except the latter adds a layer of indirection via the sim state. This
lets models set up different functions at runtime and doesn't reach so
directly into the arch-specific cpu state.
It also doesn't make sense to have two sets of macros that do exactly
the same thing, so lets standardize on the one that gets us more.
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This makes the common sim-cpu logic work.
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This makes the common sim-cpu logic work.
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Now that all the targets are utilizing CPU_PC_{FETCH,STORE}, and the
cpu state is multicore, and the STATE_CPU defines match, we can move
it all to the common code.
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This sets up the sim_state structure and the cpu member to match what we
do in most other sims, and what the common code suggests. This is a step
to unifying on the sim-cpu.o object.
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The common sim code has switched to using gdb directly; update the
ppc copy too.
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This should be SIM, not GDB.
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The old run frontend had a --version option, but the new common
sim-options file does not. Restore support for that so we can
get version info out of `run` when using the new frontend.
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Since the local create-version.sh already points directly into the gdb
source tree, we might as well use the gdb script directly too.
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Make cpu allocation fully dynamic so we can leverage the common
sim-cpu and its APIs.
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Make cpu allocation fully dynamic so we can leverage the common
sim-cpu and its APIs.
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Make cpu allocation fully dynamic so we can leverage the common
sim-cpu and its APIs.
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Make cpu allocation fully dynamic so we can leverage the common
sim-cpu and its APIs.
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Convert a bunch of old style prototypes and tweak various casts
to match the function signatures.
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