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AgeCommit message (Expand)AuthorFilesLines
2021-05-29sim: mn10300: add SIGTRAP fallbackMike Frysinger2-0/+7
2021-05-29sim: pull in extra gnulib libs tooMike Frysinger2-1/+5
2021-05-29sim: mips: fix build w/out dv-sockserMike Frysinger2-3/+9
2021-05-29sim: frv: fix up a bunch of prototype warningsMike Frysinger7-6/+41
2021-05-29sim: frv: fix compiler parentheses suggestions warningsMike Frysinger4-25/+39
2021-05-29sim: sh: fix a few compiler warningsMike Frysinger2-2/+7
2021-05-29sim: m32c: rename open symbol to avoid collisionsMike Frysinger2-4/+10
2021-05-29sim: leverage gnulibMike Frysinger5-3/+33
2021-05-28sim: bfin: fix the otp fix fixMike Frysinger2-2/+6
2021-05-28sim: h8300 add special case test.Yoshinori Sato10-16/+520
2021-05-28sim: h8300 Fixed different behavior in preinc/predec.Yoshinori Sato3-3/+60
2021-05-24opcodes: cris: move desc & opc files from sim/Mike Frysinger5-3339/+13
2021-05-23sim: cris: fix memory setup typosMike Frysinger2-1/+5
2021-05-23sim: bfin: fix the otp fixMike Frysinger2-1/+7
2021-05-23sim: bfin: fix build warnings w/newer gccMike Frysinger2-1/+5
2021-05-23sim: rl78: rename open symbol to avoid collisionsMike Frysinger2-4/+10
2021-05-23sim: cris: add unistd.h for environ declMike Frysinger2-0/+5
2021-05-23sim: bfin: add strings.h for ffs()Mike Frysinger2-0/+6
2021-05-22sim: mips: Add shadow mappings for 32-bit memory address spaceFaraz Shahbazker2-3/+17
2021-05-22sim: mips: Only truncate sign extension bits for 32-bit target modelsFaraz Shahbazker2-6/+11
2021-05-21sim/d10v: Use offsetof in a static assertion about structure layout.John Baldwin2-2/+7
2021-05-20sim: ppc: fix Wpointer-sign warningTom de Vries1-1/+1
2021-05-19sim: ppc: fix some Wenum-compare warningsTom de Vries1-2/+2
2021-05-19sim: ppc: fix Wnonnull warningTom de Vries1-2/+1
2021-05-19sim: ppc: fix some more Wunused-function warningsTom de Vries1-2/+2
2021-05-19sim: ppc: fix some Wunused-function warningsTom de Vries1-84/+84
2021-05-17sim: fully merge sim_state_base into sim_stateMike Frysinger43-93/+154
2021-05-17sim: riscv: invert sim_state storageMike Frysinger4-12/+22
2021-05-17sim: h8300: invert sim_state storageMike Frysinger3-11/+32
2021-05-17sim: mips: invert sim_state storageMike Frysinger5-27/+27
2021-05-17sim: avr: invert sim_state storageMike Frysinger3-11/+23
2021-05-17sim: cgen: invert sim_state storage for cgen portsMike Frysinger17-74/+49
2021-05-17sim: bfin: invert sim_state storageMike Frysinger3-9/+12
2021-05-17sim: invert sim_state storageMike Frysinger33-124/+143
2021-05-16sim: install library header filesMike Frysinger3-37/+78
2021-05-16sim: switch config.h usage to defs.hMike Frysinger302-169/+923
2021-05-16sim: riscv: move __int128 check to configureMike Frysinger96-63/+596
2021-05-15sim: ppc: clean up various warningsMike Frysinger22-54/+122
2021-05-15sim: switch to libiberty environ.hMike Frysinger4-24/+18
2021-05-14sim: callback: convert FS interfaces to 64-bitMike Frysinger4-8/+16
2021-05-14sim: callback: convert time interface to 64-bitMike Frysinger9-21/+35
2021-05-14sim: callback: inline PTR defineMike Frysinger3-3/+8
2021-05-14sim: create header namespaceMike Frysinger70-74/+190
2021-05-12sim: clean up explicit environment build callsMike Frysinger8-48/+16
2021-05-12Fix build failure in d10v simLuis Machado2-2/+11
2021-05-08sim: h8300: clean up various warningsMike Frysinger4-8/+21
2021-05-08sim: touch modules targetMike Frysinger2-0/+5
2021-05-08sim: cgen: tweak trace formatMike Frysinger2-1/+5
2021-05-08sim: cgen: namespace mode_names a bitMike Frysinger3-3/+11
2021-05-08sim: cgen: tweak cgen_rtx_error to fix warningsMike Frysinger3-1/+8
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