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AgeCommit message (Expand)AuthorFilesLines
2015-12-26sim: cris: do not pass cpu when writing memory during initMike Frysinger2-5/+10
2015-12-26sim: standardize sim_create_inferior handling of argv a bit moreMike Frysinger18-34/+106
2015-12-26sim: aarch64: move ChangeLog contentMike Frysinger2-26/+25
2015-12-25sim: frv: punt WITH_DEVICE supportMike Frysinger6-95/+10
2015-12-25sim: m32r: migrate from WITH_DEVICES to WITH_HWMike Frysinger12-178/+361
2015-12-25sim: cris: migrate from WITH_DEVICES to WITH_HWMike Frysinger10-126/+113
2015-12-25sim: cris: clean up rvdummy a bitMike Frysinger2-2/+6
2015-12-25sim: cris: set up sane default path to rvdummyMike Frysinger2-1/+14
2015-12-25sim: hw-properties: delete trace callsMike Frysinger2-4/+8
2015-12-25sim: drop WITH_ENGINE defineMike Frysinger3-15/+5
2015-12-25sim: sim-model: build for everyoneMike Frysinger29-49/+75
2015-12-25sim: move MACH/MODEL types into SIM_xxx namespaceMike Frysinger33-116/+172
2015-12-25sim: arm: delete unused codeMike Frysinger23-3651/+34
2015-12-25sim: move WITH_SCACHE_PBB to sim-main.hMike Frysinger18-49/+57
2015-12-25sim: device_error: puntMike Frysinger12-52/+32
2015-12-25sim: always enable callback memoryMike Frysinger4-13/+13
2015-12-25sim: dv-pal: always use CPU_INDEXMike Frysinger2-5/+7
2015-12-24sim: mips: delete TARGET_TX3904 defineMike Frysinger3-2/+5
2015-12-24sim: mips: move SIM_QUIET_NAN_NEGATED to sim-main.hMike Frysinger3-4/+8
2015-12-24sim: make LMA loading the default for all targetsMike Frysinger25-42/+72
2015-12-24sim: cris: move option install to sim_openMike Frysinger5-19/+18
2015-12-24sim: delete old breakpoint codeMike Frysinger11-83/+26
2015-12-24sim: h8300: move h8300-specific options out of common codeMike Frysinger5-34/+69
2015-12-24sim: enable watchpoint module everywhereMike Frysinger18-35/+37
2015-12-24sim: delete SIM_HAVE_FLATMEM supportMike Frysinger6-54/+13
2015-12-24sim: delete SIM_HAVE_MEM_SIZEMike Frysinger8-28/+16
2015-12-24sim: delete SIM_HAVE_SIMCACHEMike Frysinger6-18/+12
2015-12-15Fix invalid left shift of negative valueDominik Vogt11-33/+55
2015-12-15Add support for the MRS instruction to the AArch64 simulator.Nick Clifton2-9/+53
2015-12-07Add support for MSP430 F5 hardware multiply.Nick Clifton2-10/+59
2015-11-24Add an AArch64 simulator to GDB.Nick Clifton23-4/+31400
2015-11-22sim: common: set up CPPFLAGS/CXXFLAGS/LDFLAGS from configure [PR sim/18762]Mike Frysinger2-0/+8
2015-11-22sim: sim_do_commandf: fix call to va_end [PR sim/19273]Mike Frysinger2-2/+13
2015-11-22sim: ppc: avoid use of $< in ordinary rules [PR sim/13834]Mike Frysinger2-5/+13
2015-11-22sim: common: add PRI printf definesMike Frysinger2-0/+28
2015-11-22sim: avr: move global state to sim/cpu stateMike Frysinger3-134/+157
2015-11-22sim: avr: switch to common sim-regMike Frysinger2-4/+14
2015-11-22sim: sh: delete global callback/argvMike Frysinger3-46/+53
2015-11-22sim: h8300: delete global callback/kind/nameMike Frysinger2-47/+27
2015-11-22sim: mn10300: drop global callback handleMike Frysinger3-7/+8
2015-11-17sim: mn10300/v850: drop unused WITH_CORE defineMike Frysinger4-2/+8
2015-11-17sim: always enable modulo memoryMike Frysinger12-36/+30
2015-11-17[sim/ppc] Fix printf_filtered referencePedro Alves2-16/+21
2015-11-17sim: sim-close: use XCONCAT2 helperMike Frysinger2-3/+6
2015-11-16sim: sim-stop/sim-reason/sim-reg: move to common obj listMike Frysinger44-56/+119
2015-11-15sim: cr16: drop global callback stateMike Frysinger4-62/+70
2015-11-15sim: cr16: convert to common sim engine logicMike Frysinger5-157/+96
2015-11-15sim: cr16: convert to common sim memory modulesMike Frysinger8-589/+62
2015-11-15sim: cr16: push down sd/cpu varsMike Frysinger6-788/+833
2015-11-15sim: cr16: delete unused memory helpersMike Frysinger3-20/+6
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