aboutsummaryrefslogtreecommitdiff
path: root/sim
AgeCommit message (Collapse)AuthorFilesLines
2023-12-10Improve performance of the H8 simulatorJeff Law1-2/+96
Running the H8 port through the GCC testsuite currently takes 4h 30m on my fastest server -- that's roughly 1.5hrs per multilib tested and many tests are disabled for various reasons. To put that 1.5hr/multilib in perspective, that's roughly 3X the time for other embedded targets. Clearly something isn't working as well as it should. A bit of digging with perf shows that we're spending a crazy amount of time decoding instructions in the H8 simulator. It's not hard to see why -- basically we take a blob of instruction data, then try to match it to every instruction in the H8 opcode table starting at the beginning. That table has ~8000 entries (each different addressing mode is considered a different instruction in the table). Naturally my first thought was to sort the table and use a binary search to find the right entry. That's made excessively complex due to the encoding on the H8. Just getting the sort right would be much more complex than I'd consider advisable. Another thought was to build a mapping to the right entry for all the instructions that can be disambiguated based on the first nibble (4 bits) of instruction data and a mapping for those which can be disambiguated based on the first byte of instruction data. That seemed feasible until I realized that the H8/SX did some truly horrid things with encoding branches in the 0x4XYY opcode space. It uses an "always zero" bit in the offset to encode new semantic information. So we can't select on just 0x4X. Ugh! We could always to a custom decoder. I've done several through the years, they can be very fast. But no way I can justify the time to do that. So what I settled on was to first sort the opcode table by the first nibble, then find the index of the first instruction for each nibble. Decoding uses that index to start its search. This cuts the overall build/test by more than half. Next I adjusted the sort so that instructions that are not available on the current sub architecture are put at the end of the table. This shaves another ~15% off the total cycle time. The net of the two changes is on my fastest server we've gone from 4:30 to 1:40 running the GCC testsuite. Same test results before/after, of course. It's still not fast, but it's a hell of a lot better.
2023-12-07sim: aarch64: fix -Wunused-but-set-variable warningsMike Frysinger1-2/+1
2023-12-07sim: common: fix -Wunused-but-set-variable warningsMike Frysinger1-2/+0
2023-12-07sim: ppc: fix -Wunused-but-set-variable warningsMike Frysinger1-2/+0
2023-12-07sim: v850: fix -Wunused-but-set-variable warningsMike Frysinger2-11/+8
2023-12-07sim: sh: fix -Wunused-but-set-variable warningsMike Frysinger1-2/+0
2023-12-07sim: msp430: fix -Wunused-but-set-variable warningsMike Frysinger1-2/+1
2023-12-07sim: mips: fix -Wunused-but-set-variable warningsMike Frysinger1-3/+5
2023-12-07sim: mcore: fix -Wunused-but-set-variable warningsMike Frysinger1-4/+0
2023-12-07sim: m68hc11: fix -Wunused-but-set-variable warningsMike Frysinger2-6/+0
2023-12-07sim: h8300: fix -Wunused-but-set-variable warningsMike Frysinger1-8/+0
2023-12-07sim: ft32: fix -Wunused-but-set-variable warningsMike Frysinger1-4/+0
2023-12-07sim: frv: fix -Wunused-but-set-variable warningsMike Frysinger3-15/+0
2023-12-07sim: erc32: fix -Wunused-but-set-variable warningsMike Frysinger2-15/+4
2023-12-07sim: d10v: fix -Wunused-but-set-variable warningsMike Frysinger1-2/+2
2023-12-07sim: cris: fix -Wunused-but-set-variable warningsMike Frysinger3-4/+9
We suppress the warning in the generated switch file because the cris cpu file has a hack to workaround a cgen bug, but that generates a set but unused variable which makes the compiler upset.
2023-12-07sim: bfin: fix -Wunused-but-set-variable warningsMike Frysinger7-23/+7
2023-12-07sim: bfin: gui: fix -Wunused-but-set-variable warningsMike Frysinger1-12/+22
Rework the code to use static inline functions when it's disabled rather than macros so the compiler knows the various function args are always used. The ifdef macros are a bit ugly, but get the job done without duplicating the function prototypes.
2023-12-07sim: arm: fix -Wunused-but-set-variable warningsMike Frysinger1-2/+0
2023-12-07sim: m32r: fix syslog callMike Frysinger1-1/+2
The function returns void, not int. We only pass one argument to syslog (the format), so use %s as the static format instead since the emulation layer doesn't handle passing additional arguments.
2023-12-07sim: m32r: include more glibc headers for the funcs we use [PR sim/29752]Mike Frysinger1-0/+5
Not exactly portable, but doesn't make the situation worse here, and fixes a lot of implicit function warnings. Bug: https://sourceware.org/PR29752
2023-12-07sim: m32r: add more cgen prototypes for trapsMike Frysinger1-0/+12
The traps file uses a bunch of functions directly without prototypes, and we can't safely include the relevant cpu*.h files for them.
2023-12-07sim: m32r: add more cgen prototypes to enable -Werror in most filesMike Frysinger3-24/+27
2023-12-07sim: warnings: disable -Wenum-conversion fow now [PR sim/29752]Mike Frysinger2-0/+4
The cgen code mixes virtual insn enums with insn enums, and there isn't an obvious (to me) way to unravel this atm, so disable the warning. sim/lm32/decode.c:45:5: error: implicit conversion from enumeration type 'CGEN_INSN_VIRTUAL_TYPE' to different enumeration type 'CGEN_INSN_TYPE' (aka 'enum cgen_insn_type') [-Werror,-Wenum-conversion] 45 | { VIRTUAL_INSN_X_INVALID, LM32BF_INSN_X_INVALID, LM32BF_SFMT_EMPTY }, | ~ ^~~~~~~~~~~~~~~~~~~~~~ Bug: https://sourceware.org/PR29752
2023-12-06sim: support dlopen in -lcMike Frysinger2-2/+2
Stop assuming that dlopen is only available via -ldl. Newer versions of glibc have merged it into -lc which broke this configure test.
2023-12-06sim: cris: move generated file to right placeMike Frysinger2-14121/+1
Not sure why this ended up in the topdir, but it belongs under cris/.
2023-12-06sim: warnings: add more flagsMike Frysinger2-8/+37
Sync with the list of flags from gdbsupport, and add a few more of our own to catch recent issues. Comment out the C++-specific flags as we don't build with C++.
2023-12-05sim: warnings: sync some build logic from gdbsupportMike Frysinger2-15/+65
This fixes testing of -Wno flags, and adds some more portable ones.
2023-12-05sim: mips: fix sim_fpu usageMike Frysinger1-4/+4
Fix some of the sim_fpu calls to use the right types. While I'm not familiar with the MIPS ISA in these cases, these look like simple oversights due to the name/type mismatches. This at least fixes compiling with -Wenum-conversion.
2023-12-05sim: sh: trim trailing whitespace in generated codeMike Frysinger1-15/+15
No functional change here, but makes it a little easier to read the generated code when editors aren't highlighting all the spurious trailing whitespace on lines.
2023-12-05sim: mn10300: fix sim_engine_halt callMike Frysinger1-1/+2
The sim_stop argument is an enum and should only be one of those values, not a signal constant. Fix the logic to pass the right sim_xxx & SIM_xxx values in the right arguments.
2023-12-05sim: m32c: use UTF-8 encodingMike Frysinger1-1/+1
We only support UTF-8 nowadays, so stop using ISO-8859-1. Maybe we should delete this logic entirely, but for now, do the bare min conversion to keep it compiling.
2023-12-04sim: rx: mark unused static var as unusedMike Frysinger1-0/+1
This seems like a useful utility func that mirrors the int2float helper, so mark it as unused rather than delete.
2023-12-04sim: rx: constify some read-only global varsMike Frysinger1-3/+3
2023-12-04sim: warnings: enable only for development buildsMike Frysinger5-5/+13
Reuse the bfd/development.sh script like most other project to determine whether the current source tree is a dev build (e.g. git) or a release build, and disable the warnings for releases.
2023-12-04sim: ppc: fix implicit enum conversionMike Frysinger1-3/+3
This code tries to use attach_type enums as hw_phb_decode, and while they're setup to have compatible values, the compiler doesn't like it when the cast is missing. So cast it explicitly and then use that. sim/ppc/hw_phb.c:322:28: error: implicit conversion from enumeration type 'attach_type' (aka 'enum _attach_type') to different enumeration type 'hw_phb_decode' [-Werror,-Wenum-conversion]
2023-12-04sim: ppc: fix -Wmisleading-indentation warningsMike Frysinger1-1/+1
Fix building with -Wmisleading-indentation.
2023-12-04sim: ppc: cleanup getrusage declsMike Frysinger3-17/+2
Don't conflate HAVE_GETRUSAGE & HAVE_SYS_RESOURCE_H. Use the latter to include the header and nothing else. Use the former to determine whether to use the function and nothing else. If we find a system that doesn't follow POSIX and provides only one of these, we can figure out how to support it then. The manual local definition is clashing with the system ones and leading to build failures with newer C standards. sim/ppc/emul_netbsd.c:51:5: error: a function declaration without a prototype is deprecated in all versions of C and is treated as a zero-parameter prototype in C2x, conflicting with a previous declaration [-Werror,-Wdeprecated-non-prototype]
2023-12-01Fix right shifts in mcore simulator on 64 bit hosts.Jeff Law3-2/+55
If the value to be shifted has the sign bit set, the sign bit would get copied into bits 32..63 of the temporary. Those would then be right shifted into the final value giving an incorrect final result. This was observed with upcoming GCC improvements which eliminate unnecessary extensions.
2023-11-28sim: bpf: do not use semicolon to begin commentsJose E. Marchesi11-292/+292
The BPF assembler has been updated to follow the clang convention in the interpretation of semicolons: they separate statements and directives, and do not start line comments.
2023-11-16sim: mips: Change E_MIPS_* to EF_MIPS_*Ying Huang1-2/+2
According to we have changed all E_MIPS_* to EF_MIPS_* in binutils and glibc, we also need to change it here to keep same style. We can refer to this commit record: https://sourceware.org/pipermail/binutils/2023-October/129904.html Approved-By: Pedro Alves <pedro@palves.net>
2023-10-18sim/riscv: fix JALR instruction simulationJaydeep Patil3-4/+32
Fix 32bit 'jalr rd,ra,imm' integer instruction, where RD was written before using it to calculate destination address. This commit also improves testutils.inc for riscv; make use of pushsection and popsection when adding things to .data, and setup the %gp global pointer register within the 'start' macro. Approved-By: Andrew Burgess <aburgess@redhat.com>
2023-10-15sim: mips: fix printf stringMike Frysinger1-1/+1
2023-10-11[RFA] Fix for mcore simulatorJeff Law3-4/+56
I was looking for cases where a GCC patch under evaluation would cause test results to change. Quite surprisingly the mcore-elf port showed test differences. After a fair amount of digging my conclusion was the sequences before/after the patch should have been semantically the same. Of course if the code is supposed to behave the same, then that points to problems elsewhere (assembler, linker, simulator). Sure enough the mcore simulator was mis-handling the sign extension instructions. The simulator implementation of sextb is via paired shift-by-24 operations. Similarly the simulator implements sexth via paired shift-by-16 operations. The temporary holding the value was declared as a "long" thus this approach worked fine for hosts with a 32 bit wide long and failed miserably for hosts with a 64 bit wide long. This patch makes the shift count automatically adjust based on the size of the temporary. It includes a simple test for sextb and sexth. I have _not_ done a full audit of the mcore simulator for more 32->64 bit issues. This also fixes 443 execution tests in the GCC testsuite
2023-08-26Simplify definition of GUILETom Tromey3-6/+2
This patch sets GUILE to just plain 'guile'. In the distant ("devo") past, the top-level build did support building Guile in-tree. However, I don't think this really works any more. For one thing, there are no build dependencies on it, so there's no guarantee it would actually be built before the uses. This patch also removes the use of "-s" as an option to cgen scheme scripts. With my latest patch upstream, this is no longer needed. After the upstream changes, either Guile 2 or Guile 3 will work, with or without the compiler enabled. 2023-08-24 Tom Tromey <tom@tromey.com> * cgen.sh: Don't pass "-s" to cgen. * Makefile.in: Rebuild. * Makefile.am (GUILE): Simplify.
2023-08-24sim: or1k: Eliminate dangerous RWX load segmentsStafford Horne5-8/+10
This fixes test failures caused by the new linker warning which report: ./ld/ld-new: warning: load.S.x has a LOAD segment with RWX permissions Fix this by splitting the linker MEMORY into ram and rom to avoid generating RWX sections. This required tests to be adjusted to fix issues with the move. Namely: - fpu tests: were incorrectly using l.ori with ha(anchor) which now that we pushed the anchor up in memory it exposes the bug. Update to used the correct l.movhi instruction instead. - adrp test: the test reports ram offset addresses, now that we have moved memory layout around a bit I adjusted the test output. Some padding is added before pi to show that the actual address of pi and the adrp page offset are not the same. Bug: https://sourceware.org/PR29957
2023-08-21sim: bpf: remove negi, neg32i insnsDavid Faust1-8/+0
The BPF virtual machine does not support neg instructions operating on immediates, and these erroneous instructions were recently removed from gas. Remove them from the simulator as well.
2023-08-19Placate -Wmissing-declarations in sim/crisTom Tromey1-0/+10
I get a couple of -Wmissing-declarations errors when building the sim. This happens because an earlier patch added the declarations to a cgen-generated header, but the recent re-generation then removed them. This patch fixes the build by adding declarations just before the definition. This is normally not best practice, but in this particular situation it at leat un-breaks the build.
2023-08-19Remove extraneous '%' from sim/cris/local.mkTom Tromey2-2/+2
I saw this warning from make: Makefile:5043: *** mixed implicit and normal rules: deprecated syntax I believe this snuck in by error with the recent cgen-related changes. This patch removes the stray '%' and rebuilds the Makefile.in. I'm checking this in.
2023-08-19sim regenAlan Modra70-357/+14594
This regenerates sim files. Tested with the following tools from a recent binutils build in sim-site-config.exp, plus a few cross compilers. set AS_FOR_TARGET_AARCH64 "/home/alan/build/gas/aarch64-linux-gnu/gas/as-new" set LD_FOR_TARGET_AARCH64 "/home/alan/build/gas/aarch64-linux-gnu/ld/ld-new" set CC_FOR_TARGET_AARCH64 "aarch64-linux-gnu-gcc" set AS_FOR_TARGET_ARM "/home/alan/build/gas/arm-linux-gnueabi/gas/as-new" set LD_FOR_TARGET_ARM "/home/alan/build/gas/arm-linux-gnueabi/ld/ld-new" set CC_FOR_TARGET_ARM "arm-linux-gnueabi-gcc" set AS_FOR_TARGET_AVR "/home/alan/build/gas/avr-elf/gas/as-new" set LD_FOR_TARGET_AVR "/home/alan/build/gas/avr-elf/ld/ld-new" set CC_FOR_TARGET_AVR "" set AS_FOR_TARGET_BFIN "/home/alan/build/gas/bfin-elf/gas/as-new" set LD_FOR_TARGET_BFIN "/home/alan/build/gas/bfin-elf/ld/ld-new" set CC_FOR_TARGET_BFIN "" set AS_FOR_TARGET_BPF "/home/alan/build/gas/bpf-none/gas/as-new" set LD_FOR_TARGET_BPF "/home/alan/build/gas/bpf-none/ld/ld-new" set CC_FOR_TARGET_BPF "" set AS_FOR_TARGET_CR16 "/home/alan/build/gas/cr16-elf/gas/as-new" set LD_FOR_TARGET_CR16 "/home/alan/build/gas/cr16-elf/ld/ld-new" set CC_FOR_TARGET_CR16 "" set AS_FOR_TARGET_CRIS "/home/alan/build/gas/cris-elf/gas/as-new" set LD_FOR_TARGET_CRIS "/home/alan/build/gas/cris-elf/ld/ld-new" set CC_FOR_TARGET_CRIS "" set AS_FOR_TARGET_D10V "/home/alan/build/gas/d10v-elf/gas/as-new" set LD_FOR_TARGET_D10V "/home/alan/build/gas/d10v-elf/ld/ld-new" set CC_FOR_TARGET_D10V "" set AS_FOR_TARGET_FRV "/home/alan/build/gas/frv-elf/gas/as-new" set LD_FOR_TARGET_FRV "/home/alan/build/gas/frv-elf/ld/ld-new" set CC_FOR_TARGET_FRV "" set AS_FOR_TARGET_FT32 "/home/alan/build/gas/ft32-elf/gas/as-new" set LD_FOR_TARGET_FT32 "/home/alan/build/gas/ft32-elf/ld/ld-new" set CC_FOR_TARGET_FT32 "" set AS_FOR_TARGET_H8300 "/home/alan/build/gas/h8300-elf/gas/as-new" set LD_FOR_TARGET_H8300 "/home/alan/build/gas/h8300-elf/ld/ld-new" set CC_FOR_TARGET_H8300 "" set AS_FOR_TARGET_IQ2000 "/home/alan/build/gas/iq2000-elf/gas/as-new" set LD_FOR_TARGET_IQ2000 "/home/alan/build/gas/iq2000-elf/ld/ld-new" set CC_FOR_TARGET_IQ2000 "" set AS_FOR_TARGET_LM32 "/home/alan/build/gas/lm32-linux-gnu/gas/as-new" set LD_FOR_TARGET_LM32 "/home/alan/build/gas/lm32-linux-gnu/ld/ld-new" set CC_FOR_TARGET_LM32 "" set AS_FOR_TARGET_M32C "/home/alan/build/gas/m32c-elf/gas/as-new" set LD_FOR_TARGET_M32C "/home/alan/build/gas/m32c-elf/ld/ld-new" set CC_FOR_TARGET_M32C "" set AS_FOR_TARGET_M32R "/home/alan/build/gas/m32r-elf/gas/as-new" set LD_FOR_TARGET_M32R "/home/alan/build/gas/m32r-elf/ld/ld-new" set CC_FOR_TARGET_M32R "" set AS_FOR_TARGET_M68HC11 "/home/alan/build/gas/m68hc11-elf/gas/as-new" set LD_FOR_TARGET_M68HC11 "/home/alan/build/gas/m68hc11-elf/ld/ld-new" set CC_FOR_TARGET_M68HC11 "" set AS_FOR_TARGET_MCORE "/home/alan/build/gas/mcore-elf/gas/as-new" set LD_FOR_TARGET_MCORE "/home/alan/build/gas/mcore-elf/ld/ld-new" set CC_FOR_TARGET_MCORE "" set AS_FOR_TARGET_MICROBLAZE "/home/alan/build/gas/microblaze-linux-gnu/gas/as-new" set LD_FOR_TARGET_MICROBLAZE "/home/alan/build/gas/microblaze-linux-gnu/ld/ld-new" set CC_FOR_TARGET_MICROBLAZE "microblaze-linux-gnu-gcc" set AS_FOR_TARGET_MIPS "/home/alan/build/gas/mips-linux-gnu/gas/as-new" set LD_FOR_TARGET_MIPS "/home/alan/build/gas/mips-linux-gnu/ld/ld-new" set CC_FOR_TARGET_MIPS "mips-linux-gnu-gcc" set AS_FOR_TARGET_MN10300 "/home/alan/build/gas/mn10300-elf/gas/as-new" set LD_FOR_TARGET_MN10300 "/home/alan/build/gas/mn10300-elf/ld/ld-new" set CC_FOR_TARGET_MN10300 "" set AS_FOR_TARGET_MOXIE "/home/alan/build/gas/moxie-elf/gas/as-new" set LD_FOR_TARGET_MOXIE "/home/alan/build/gas/moxie-elf/ld/ld-new" set CC_FOR_TARGET_MOXIE "" set AS_FOR_TARGET_MSP430 "/home/alan/build/gas/msp430-elf/gas/as-new" set LD_FOR_TARGET_MSP430 "/home/alan/build/gas/msp430-elf/ld/ld-new" set CC_FOR_TARGET_MSP430 "" set AS_FOR_TARGET_OR1K "/home/alan/build/gas/or1k-linux-gnu/gas/as-new" set LD_FOR_TARGET_OR1K "/home/alan/build/gas/or1k-linux-gnu/ld/ld-new" set CC_FOR_TARGET_OR1K "" set AS_FOR_TARGET_PPC "/home/alan/build/gas/powerpc-linux-gnu/gas/as-new" set LD_FOR_TARGET_PPC "/home/alan/build/gas/powerpc-linux-gnu/ld/ld-new" set CC_FOR_TARGET_PPC "powerpc-linux-gnu-gcc" set AS_FOR_TARGET_PRU "/home/alan/build/gas/pru-elf/gas/as-new" set LD_FOR_TARGET_PRU "/home/alan/build/gas/pru-elf/ld/ld-new" set CC_FOR_TARGET_PRU "" set AS_FOR_TARGET_RISCV "/home/alan/build/gas/riscv32-elf/gas/as-new" set LD_FOR_TARGET_RISCV "/home/alan/build/gas/riscv32-elf/ld/ld-new" set CC_FOR_TARGET_RISCV "" set AS_FOR_TARGET_RL78 "/home/alan/build/gas/rl78-elf/gas/as-new" set LD_FOR_TARGET_RL78 "/home/alan/build/gas/rl78-elf/ld/ld-new" set CC_FOR_TARGET_RL78 "" set AS_FOR_TARGET_RX "/home/alan/build/gas/rx-elf/gas/as-new" set LD_FOR_TARGET_RX "/home/alan/build/gas/rx-elf/ld/ld-new" set CC_FOR_TARGET_RX "" set AS_FOR_TARGET_SH "/home/alan/build/gas/sh-rtems/gas/as-new" set LD_FOR_TARGET_SH "/home/alan/build/gas/sh-rtems/ld/ld-new" set CC_FOR_TARGET_SH "" set AS_FOR_TARGET_ERC32 "" set LD_FOR_TARGET_ERC32 "" set CC_FOR_TARGET_ERC32 "" set AS_FOR_TARGET_V850 "/home/alan/build/gas/v850-elf/gas/as-new" set LD_FOR_TARGET_V850 "/home/alan/build/gas/v850-elf/ld/ld-new" set CC_FOR_TARGET_V850 "" Results both before and after were: FAIL: crisv10 mem1.ms (execution) FAIL: crisv10 mem2.ms (execution) FAIL: crisv32 mem1.ms (execution) FAIL: crisv32 mem2.ms (execution) FAIL: microblaze fail.s (execution) FAIL: microblaze pass.s (execution) expected passes 5288 unexpected failures 6 expected failures 3 untested testcases 373 unsupported tests 14
generated by cgit v1.1 at 2024-07-24 20:53:23 +0000