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AgeCommit message (Expand)AuthorFilesLines
2021-07-08sim: erc32: use libsim.a for common objectsMike Frysinger1-2/+2
2021-07-06sim: ppc: add missing empty targetsDan Streetman1-0/+12
2021-07-01sim: unify reserved instruction bits settingsMike Frysinger33-140/+100
2021-07-01sim: m32r: merge with common configure scriptMike Frysinger8-2902/+35
2021-07-01sim: m32r: reformat linux traps codeMike Frysinger2-1067/+1067
2021-07-01sim: m32r: unify ELF & Linux traps logicMike Frysinger8-1385/+1207
2021-07-01sim: m32r: replace custom endian helpers with sim-endianMike Frysinger2-107/+90
2021-07-01sim: m32r: fix virtual environment with Linux targetsMike Frysinger5-8/+15
2021-07-01sim: m32r: namespace Linux syscall tableMike Frysinger3-370/+377
2021-07-01cgen: split GUILE setting outMike Frysinger2-1/+7
2021-06-30sim: ppc: unify (most) compiler warnings with common codeMike Frysinger3-5/+73
2021-06-30sim: cris/frv/iq2000/lm32: merge with common configure scriptMike Frysinger21-11650/+185
2021-06-30sim: unify scache settingsMike Frysinger45-254/+109
2021-06-30sim: frv: scope the unique configure flagMike Frysinger4-29/+41
2021-06-30sim: move scache init to dynamic modules.cMike Frysinger4-7/+12
2021-06-30sim: move profile init to dynamic modules.cMike Frysinger4-8/+11
2021-06-30sim: move trace init to dynamic modules.cMike Frysinger4-8/+11
2021-06-30sim: move engine init to dynamic modules.cMike Frysinger4-6/+10
2021-06-30sim: bfin: merge with common configure scriptMike Frysinger8-2912/+43
2021-06-30sim: delete unused model settingsMike Frysinger2-23/+6
2021-06-30sim: move default model to the runtime sim stateMike Frysinger62-298/+120
2021-06-30sim: namespace sim_machsMike Frysinger35-46/+167
2021-06-29sim: ppc: fix printf warningsMike Frysinger3-2/+16
2021-06-29sim: use -Wunused-but-set-parameterMike Frysinger3-12/+25
2021-06-29sim: fix arch Makefile regen when unifiedMike Frysinger2-1/+7
2021-06-29sim: use -Wno-error=maybe-uninitializedMike Frysinger3-0/+9
2021-06-29sim: callback: add check for HAVE_KILLMike Frysinger2-0/+9
2021-06-29sim: cris: remove cgen-ops.h include hackMike Frysinger2-4/+5
2021-06-29sim: model: constify sim_machs storageMike Frysinger21-15/+60
2021-06-29sim: io: add printf attributes to vprintf funcs tooMike Frysinger2-2/+9
2021-06-29sim: callback: add printf attributesMike Frysinger2-1/+7
2021-06-29sim: callback: drop unused printf helpersMike Frysinger3-66/+8
2021-06-29sim: cgen: require long long supportMike Frysinger3-29/+6
2021-06-28sim: bpf: enable -Werror usageMike Frysinger2-3/+4
2021-06-28sim: bpf: fix printf warnings on 32-bit systemsMike Frysinger2-1/+5
2021-06-28sim: cgen: delete unused record_trace_results functionsMike Frysinger17-80/+31
2021-06-27sim: frv: add missing const typeMike Frysinger2-1/+5
2021-06-27sim: frv: fix engine hookMike Frysinger2-1/+5
2021-06-27sim: frv: fix up various missing prototype warningsMike Frysinger6-1/+22
2021-06-27sim: frv: fix some printf type mismatch warningsMike Frysinger3-2/+7
2021-06-27sim: frv: fix uninitialized variable warningMike Frysinger2-2/+6
2021-06-27sim: frv: fix return type for post_wait_for funcsMike Frysinger3-19/+31
2021-06-27sim: frv: fix ambiguous else compiler warningsMike Frysinger4-25/+43
2021-06-27sim: bpf/cris: include cgen-mem in decodersMike Frysinger6-0/+16
2021-06-27sim: bpf: include more local headers & fix broken funcsMike Frysinger5-10/+25
2021-06-27sim: cgen: suppress trace non-literal printf warningMike Frysinger2-0/+10
2021-06-27sim: cgen: add asserts to fix unused engine warningsMike Frysinger2-1/+8
2021-06-27sim: cgen: add printf attributes in a few more callsMike Frysinger2-2/+7
2021-06-27sim: cgen: constify trace stringsMike Frysinger3-8/+17
2021-06-27sim: cgen: always leverage the mem prototypesMike Frysinger2-14/+55
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