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2002-03-012002-02-28 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-3/+3
* mips.igen (DSRA32, DSRAV): Fix order of arguments in instruction-printing string. (LWU): Use '64' as the filter flag.
2002-03-012002-02-28 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-1/+1
* mips.igen (SDXC1): Fix instruction-printing string.
2002-03-012002-02-28 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-4/+2
* mips.igen (LDC1, SDC1): Remove mipsI model, and mark with filter flags "32,f".
2002-02-282002-02-27 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-1/+1
* mips.igen (PREFX): This is a 64-bit instruction, use '64' as the filter flag.
2002-02-282002-02-27 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-2/+3
* mips.igen (PREFX): Tweak instruction opcode fields (i.e., add a comma) so that it more closely match the MIPS ISA documentation opcode partitioning. (PREF): Put useful names on opcode fields, and include instruction-printing string.
2002-02-282002-02-27 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-0/+128
* mips.igen (check_u64): New function which in the future will check whether 64-bit instructions are usable and signal an exception if not. Currently a no-op. (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL, DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1, LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64. * mips.igen (check_fpu): New function which in the future will check whether FPU instructions are usable and signal an exception if not. Currently a no-op. (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1, LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf, MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
2002-02-272002-02-27 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-156/+153
* mips.igen (do_load_left, do_load_right): Move to be immediately following do_load. (do_store_left, do_store_right): Move to be immediately following do_store.
2002-02-272002-02-27 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-1/+188
* mips.igen (mipsV): New model name. Also, add it to all instructions and functions where it is appropriate.
2002-02-192002-02-18 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-96/+377
* mips.igen: For all functions and instructions, list model names that support that instruction one per line.
2002-02-112002-02-11 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-9/+25
* mips.igen: Add some additional comments about supported models, and about which instructions go where. (BC1b, MFC0, MTC0, RFE): Sort supported models in the same order as is used in the rest of the file.
2002-02-112002-02-11 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-7/+6
* mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment indicating that ALU32_END or ALU64_END are there to check for overflow. (DADD): Likewise, but also remove previous comment about overflow checking.
2002-02-112002-02-10 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-48/+48
* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU, JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU, SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI, ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode fields (i.e., add and move commas) so that they more closely match the MIPS ISA documentation opcode partitioning.
2002-02-112002-02-10 Chris Demetriou cgd@sibyte.comChris Demetriou1-6/+10
* mips.igen (ADDI): Print immediate value. (BREAK): Print code. (DADDIU, DSRAV, DSRLV): Print correct instruction name. (SLL): Print "nop" specially, and don't run the code that does the shift for the "nop" case.
2001-04-12* mips.igen (CFC1, CTC1): Pass the correct register numbers toJim Blandy1-3/+3
PENDING_FILL. Use PENDING_SCHED directly to handle the pending set of the FCSR. * sim-main.h (COCIDX): Remove definition; this isn't supported by PENDING_FILL, and you can get the intended effect gracefully by calling PENDING_SCHED directly.
2000-07-04Fix MOVN.fmt and MOVZ.fmt, need to test GPR[RT].Andrew Cagney1-14/+9
2000-06-23Fix printf arguments.Andrew Cagney1-3/+4
2000-05-29fix spelling mistake in commentNick Clifton1-1/+1
2000-05-01* mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.Andrew Cagney1-1/+2
2000-03-02* autoconf correctionFrank Ch. Eigler1-3/+19
* merge from internal repo -> sourceware 2000-03-02 Frank Ch. Eigler <fche@redhat.com> * configure: Regenerated. Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com> * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf calls, conditional on the simulator being in verbose mode.
1999-12-07import gdb-1999-12-06 snapshotJason Molenda1-0/+2
1999-10-26import gdb-1999-10-25 snapshotJason Molenda1-4/+3
1999-09-13import gdb-1999-09-13 snapshotJason Molenda1-2/+2
1999-09-09import gdb-1999-09-08 snapshotStan Shebs1-1/+2
1999-07-07import gdb-1999-07-07 pre reformatJason Molenda1-0/+18
1999-04-26import gdb-19990422 snapshotStan Shebs1-1/+9
1999-04-16Initial creation of sourceware repositorygdb-4_18-branchpointStan Shebs1-0/+3895
1999-04-16Initial creation of sourceware repositoryStan Shebs1-6517/+0
1998-12-30* eCos->devo merge; tx3904 sanitize tags removedFrank Ch. Eigler1-47/+95
1998-12-29 Frank Ch. Eigler <fche@cygnus.com> * interp.c (sim_open): Allocate jm3904 memory in smaller chunks. (load_word): Call SIM_CORE_SIGNAL hook on error. (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before starting. For exception dispatching, pass PC instead of NULL_CIA. (decode_coproc): Use COP0_BADVADDR to store faulting address. * sim-main.h (COP0_BADVADDR): Define. (SIM_CORE_SIGNAL): Define hook to call mips_core_signal. (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*(). (_sim_cpu): Add exc_* fields to store register value snapshots. * mips.igen (*): Replace memory-related SignalException* calls with references to SIM_CORE_SIGNAL hook. * dv-tx3904irc.c (tx3904irc_port_event): printf format warning fix. * sim-main.c (*): Minor warning cleanups.
1998-12-13for bfd:Gavin Romig-Koch1-6/+499
* archures.c,bfd-in2.h (bfd_mach_mips4121): New. * cpu-mips.c: Added vr4121. * elf32-mips.c (elf_mips_mach): Same. (_bfd_mips_elf_final_write_processing): Same. for gas: * config/tc-mips.c (mips_4121): New. (md_begin,mips_ip,md_longopts,md_parse_option): Add vr4121. for gcc: * config/mips/mips.c (override_options): Add vr4121. * config/mips/t-vr4xxx (MULTILIB_MATCHES): Same. for include/elf: * mips.h (E_MIPS_MACH_4121): New. for include/opcode: * mips.h (INSN_4121): New. for opcodes: * mips-dis.c (set_mips_isa_type): Add bfd_mach_mips4121. (_print_insn_mips): Same. * mips-opc.c: Add vr4121. for sim/mips: * configure.in,mips.igen,vr.igen: Add vr4121. * configure: Rebuilt.
1998-12-12 * configure.in (mips64vr4xxx): Enable TARGET_ENABLE_FR.Gavin Romig-Koch1-2/+2
Set mips_fpu, and mips_fpu_bitsize. Set sim_gen, and sim_igen_machine. * configure: Rebuild. * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts. * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1998-12-08* sky->devo merge, final part of sim mergeFrank Ch. Eigler1-4/+205
[ChangeLog.sky] 1998-12-08 Frank Ch. Eigler <fche@cygnus.com> * sim-main.h (sim_state): Add multi-phase load tracking fields. * sky-gdb.c (sky_option_handler): Add --load-next option handling. * mips.igen (BREAK): Add multi-phase load and printf code handling.
1998-11-23Configure mips64vr4100-elf nee mips64vr41* as a 64 bit mips16 igen simulator.Andrew Cagney1-0/+3
Fix problems: All vr.igen instructions are 64 bit.
1998-11-23Switch mips-lsi-elf mips16 simulator to igen (from gencode).Andrew Cagney1-432/+476
1998-06-29 * mips.igen (check_mf_hilo): Correct check.Gavin Romig-Koch1-104/+5
1998-06-18* Adapt to changed R5900 SQC2 opcode.Frank Ch. Eigler1-19/+46
Thu Jun 18 17:48:01 1998 Frank Ch. Eigler <fche@cygnus.com> * mips.igen (SDC2): Removed R5900 alternative. * r5900.igen (SQC2): Updated bit pattern to match changed R5900 specs.
1998-06-16* ECC (tx39) and sky changes.Frank Ch. Eigler1-13/+19
[ChangeLog] start-sanitize-tx3904 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com> * dv-tx3904tmr.c: Deschedule timer event after dispatching. Reduce unnecessarily high timer event frequency. * dv-tx3904cpu.c: Ditto for interrupt event. end-sanitize-tx3904 start-sanitize-sky Tue Jun 16 14:12:09 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (decode_coproc): Removed COP2 branches. * r5900.igen: Moved COP2 branch instructions here. * mips.igen: Restricted COPz == COP2 bit pattern to exclude COP2 branches. end-sanitize-sky
1998-06-16Fix unresolved external error for sky_cpcond0 on non-SKY builds.James Lemke1-0/+8
1998-06-15Implement CPCOND0 and insns BC0F/BC0FL/BC0T/BC0TL.James Lemke1-0/+32
1998-06-09* Handle 10 and 20-bit versions of Break instruction. Move handlingIan Carmichael1-0/+30
* of special values from signal_exception() in interp.c into mips.igen. * * Modified: gencode.c interp.c mips.igen sim-main.h
1998-06-09 * mips.igen (SWC1) : Correct the handling of ReverseEndianGavin Romig-Koch1-6/+6
and BigEndianCPU.
1998-06-04The r5900 doesn't have HI/LO DIV/MUL register problems. HobbleAndrew Cagney1-27/+118
checks on hi/lo usage but retain functions so that they can be used for HI/LO stall counting code.
1998-05-21Fix sign extension on 32 bit add/sub instructions.Andrew Cagney1-18/+42
1998-05-18* Monster patch - may destablize MIPS sims for a little while.Frank Ch. Eigler1-0/+46
* Followup patch for SCEI PR 15853 * First check-in of TX3904 interrupt controller devices for ECC. [sanitized] * First implementation of MIPS hardware interrupt emulation. Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com> * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware modules. Recognize TX39 target with "mips*tx39" pattern. * configure: Rebuilt. * sim-main.h (*): Added many macros defining bits in TX39 control registers. (SignalInterrupt): Send actual PC instead of NULL. (SignalNMIReset): New exception type. * interp.c (board): New variable for future use to identify a particular board being simulated. (mips_option_handler,mips_options): Added "--board" option. (interrupt_event): Send actual PC. (sim_open): Make memory layout conditional on board setting. (signal_exception): Initial implementation of hardware interrupt handling. Accept another break instruction variant for simulator exit. (decode_coproc): Implement RFE instruction for TX39. (mips.igen): Decode RFE instruction as such. start-sanitize-tx3904 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904. * interp.c: Define "jmr3904" and "jmr3904debug" board types and bbegin to implement memory map. * dv-tx3904cpu.c: New file. * dv-tx3904irc.c: New file. end-sanitize-tx3904
1998-05-13 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):Gavin Romig-Koch1-9/+49
Replace check_op_hilo with check_mult_hilo and check_div_hilo. Add special r3900 version of do_mult_hilo. (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo with calls to check_mult_hilo. (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo with calls to check_div_hilo.
1998-04-21Implement ERET instruction.Andrew Cagney1-0/+20
Add {signed,unsigned}_address type.
1998-04-21For new IGEN simulators, rewrite checks validating correct use of theAndrew Cagney1-30/+96
HI/LO registers. For old gencode simulator, delete all checks.
1998-04-15Re-fix 32 bit DSRAV instruction.Andrew Cagney1-6/+15
Fix mips16 BRANCH, unsigned ADD/SUB and SRAV instructions.
1998-04-15Debug tx19 built from igen sources.Andrew Cagney1-10/+105
Rework ifetch{16,32} to match the more recent do_load function.
1998-04-14Implement 32 bit MIPS16 instructions listed in m16.igen.Andrew Cagney1-112/+297
1998-04-05* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIFFrank Ch. Eigler1-819/+193
masking facility for PATH3 transfers. [ChangeLog.sky] Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c (exec-inst): Added "M" bit detection for upper instruction. * sky-pke.c (pke_check_stall): Added more assertions. (pke_code_mskpath3): Use new GPUIF M3P control register. * sky-pke.h (VU[01]_CIA): New macros that give VU CIA pseudo-register addresses. * sky-vu.h (vu_device, VectorUnitState): Merged structs. (VectorUnitState.mflag): New field. (VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers. * sky-vu.c (vu0_busy): New function. (vu0_q_busy): New function. (vu0_macro_issue): New function. (vu0_micro_interlock_released): New function. (vu0_busy_in_{micro,macro}_mode): Deleted stubs. (vu0_macro_hazard_check): Deleted stubs. (vu_attach): Adapted code to merged device & state struct. (read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register. [ChangeLog] start-sanitize-sky Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (*): Adapt code to merged VU device & state structs. (decode_coproc): Execute COP2 each macroinstruction without pipelining, by stepping VU to completion state. Adapted to read_vu_*_reg style of register access. * mips.igen ([SL]QC2): Removed these COP2 instructions. * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here. * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards. end-sanitize-sky
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