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AgeCommit message (Expand)AuthorFilesLines
1998-04-02For mips get_mem_size call. Force the return of a 32 bit valueAndrew Cagney1-43/+0
1998-04-01* You bop one on the head ... another one appears.Frank Ch. Eigler1-0/+4
1998-03-27* Inserted skeleton of R5900 COP2 simulation. Merged old vu[01].[ch] codeFrank Ch. Eigler1-11/+611
1998-03-03Fix DIV, DIV1 (wrong check for overflow) and DIVU1 (shouldn't checkAndrew Cagney1-2/+5
1998-02-25Finish implementation of r5900 instructions.Andrew Cagney1-20/+24
1998-02-23sim-main.h: Re-arange r5900 registers so that they have their ownAndrew Cagney1-48/+45
1997-12-11 * mips.igen (MSUB): Fix to work like MADD.Jeff Law1-567/+465
1997-11-11Make the signess of compares between GPR's explicit using a cast toAndrew Cagney1-59/+36
1997-11-11Fix IGEN version of MFC0, MTC0, SWC1, LWC1, SDC1, LDC1, LWXC1,Andrew Cagney1-115/+369
1997-11-06IGEN likes to cache the current instruction address (CIA). Change theAndrew Cagney1-23/+22
1997-11-05Rewrite the MIPS simulator's memory model so that it uses the genericAndrew Cagney1-8/+8
1997-10-29common/sim-bits.h: Document ROTn macro.Andrew Cagney1-15/+12
1997-10-28Add support for 16 byte quantities to sim-endian macro H2T.Andrew Cagney1-26/+26
1997-10-27Separate r5900 specifoc and mips16 instructions.Andrew Cagney1-5156/+5
1997-10-27Add mips64vr5400 to configuration listAndrew Cagney1-1/+526
1997-10-24Checkpoint IGEN version of mips simAndrew Cagney1-152/+157
1997-10-16Checkpoint IGEN version of MIPS simulator.Andrew Cagney1-248/+218
1997-10-14Checkpoint IGEN version of MIPS simulator.Andrew Cagney1-1239/+1196
1997-10-09Snap. Gets through igen's checks.Andrew Cagney1-322/+104
1997-10-08MIPS/IGEN checkpoint - doesn't build.Andrew Cagney1-0/+9996
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