Age | Commit message (Collapse) | Author | Files | Lines |
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Remove last remenats of old gencode simulator.
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Fix numerous problems with PENDING_* code.
In old gencode simulator, don't double tick each cycle.
Add BREAK instruction to MIPS16 gencode simulator.
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* of special values from signal_exception() in interp.c into mips.igen.
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* Modified: gencode.c interp.c mips.igen sim-main.h
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HI/LO registers. For old gencode simulator, delete all checks.
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* gencode.c (MSUB): Similarly.
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address.
Pass cia into calls to sim_engine_stop so that breakpoints et.al. work.
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* configure.in: Add tx49 configury.
* configure: Update.
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BigEndianMem instead of !ByteSwapMem.
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When address translation of insn fetch fails raise exception immediatly.
Use address_word as type of all address variables (instead of unsigned64),
the former is configured as either 32 or 64 bit type.
Always compile fpu code (no #if has fpu)
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of arguments to Recip.
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endianness. Provide defaults for some tier-1 mips targets.
o Parameterize all functions with SIM_DESC.
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* gencode.c (SDBBP,DERET): Added (3900) insns.
(RFE): Turn on for 3900.
* interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
(dsstate): Made global.
(SUBTARGET_R3900): Added.
(CANCELDELAYSLOT): New.
(SignalException): Ignore SystemCall rather than ignore and
terminate. Add DebugBreakPoint handling.
(decode_coproc): New insns RFE, DERET; and new registers Debug
and DEPC protected by SUBTARGET_R3900.
(sim_engine_run): Use CANCELDELAYSLOT rather than clearing
bits explicitly.
* Makefile.in,configure.in: Add mips subtarget option.
* configure: Update.
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* gencode.c: Fix some configuration problems by improving
the relationship between tx19 and tx39.
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JALR, just 2.
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* config.sub: Add tx19/r1900.
* sim/mips/configure.in, sim/mips/gencode: Add tx19/r1900.
* gcc/config.sub, gcc/configure: Add tx19/r1900.
* gcc/config/mips/r1900.h, config/mips/t-r1900: New.
* gas/config/tc-mips.c: Add tx19/r1900.
* gcc/config/mips/mips.c: Don't build 16 bit to 32 bit stubs for
TARGET_SOFT_FLOAT.
* config.sub: Add "marketing-names" patch.
* gcc/config.sub: Add "marketing-names" patch.
* gcc/configure: Change "as" link from "../gas/as.new" to "../gas/as-new";
Same for "ld" link.
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that image properties such as endianness can be checked.
More strongly document the expected behavour of each of the sim_*
interfaces.
Add default endian argument to simulator config macro
SIM_AC_OPTION_ENDIAN. Use in sim_config.
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In particular a host endian dependency one fixed resolved most problems.
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version 1.95 of the r5900 ISA.
Fixes pr12413 (c/h from toshiba).
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version 1.95 of the r5900 ISA.
fixes pr12407 (c/h from toshiba).
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Fix for pr12402 (c/h from toshiba).
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o Take an interrupt when an int event occures.
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* gencode.c: #ifdef out offending code until a permanent fix
can be added. Code is causing build errors for non-5900 mips targets.
end-sanitize-r5900
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address for extended PC relative instruction.
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comparison flags at any ISA level, not just ISA 4.
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* gencode.c (build_instruction): Use BigEndianCPU instead of
ByteSwapMem.
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that messes up arithmetic shifts.
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force a 64 bit multiplication.
(build_instruction) [OR]: In mips16 mode, don't do anything if the
destination register is 0, since that is the default mips16 nop
instruction.
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(build_endian_shift): Don't check proc64.
(build_instruction): Always set memval to uword64. Cast op2 to
uword64 when shifting it left in memory instructions. Always use
the same code for stores--don't special case proc64.
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relative operands.
(build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
jal instruction.
* interp.c (simJALDELAYSLOT): Define.
(JALDELAYSLOT): Define.
(INDELAYSLOT, INJALDELAYSLOT): Define.
(simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
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* gencode.c (build_instruction): Use !ByteSwapMem instead of
BigEndianMem.
* interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
(BigEndianMem): Rename to ByteSwapMem and change sense.
(BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
BigEndianMem references to !ByteSwapMem.
(set_endianness): New function, with prototype.
(sim_open): Call set_endianness.
(sim_info): Use simBE instead of BigEndianMem.
(xfer_direct_word, xfer_direct_long, swap_direct_word,
swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
ifdefs, keeping the prototype declaration.
(swap_word): Rewrite correctly.
(ColdReset): Delete references to CONFIG. Delete endianness related
code; moved to set_endianness.
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* gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
* interp.c (CHECKHILO): Define away.
(simSIGINT): New macro.
(membank_size): Increase from 1MB to 2MB.
(control_c): New function.
(sim_resume): Rename parameter signal to signal_number. Add local
variable prev. Call signal before and after simulate.
(sim_stop_reason): Add simSIGINT support.
(sim_warning, sim_error, dotrace, SignalException): Define as stdarg
functions always.
(sim_warning): Delete call to SignalException. Do call printf_filtered
if logfh is NULL.
(AddressTranslation): Add #ifdef DEBUG around debugging message and
a call to sim_warning.
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16 bit instructions.
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* gencode.c (inst_type): Add mips16 instruction encoding types.
(GETDATASIZEINSN): Define.
(MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
mtlo.
(MIPS16_DECODE): New table, for mips16 instructions.
(bitmap_val): New static function.
(struct mips16_op): Define.
(mips16_op_table): New table, for mips16 operands.
(build_mips16_operands): New static function.
(process_instructions): If PC is odd, decode a mips16
instruction. Break out instruction handling into new
build_instruction function.
(build_instruction): New static function, broken out of
process_instructions. Check modifiers rather than flags for SHIFT
bit count and m[ft]{hi,lo} direction.
(usage): Pass program name to fprintf.
(main): Remove unused variable this_option_optind. Change
``*loptarg++'' to ``loptarg++''.
(my_strtoul): Parenthesize && within ||.
* interp.c (sim_trace): If tracefh is NULL, set it to stderr.
(LoadMemory): Accept a halfword pAddr if vAddr is odd.
(simulate): If PC is odd, fetch a 16 bit instruction, and
increment PC by 2 rather than 4.
* configure.in: Add case for mips16*-*-*.
* configure: Rebuild.
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(SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
* configure.in: Simplify using macros in ../common/aclocal.m4.
* configure: Regenerated.
* tconfig.in: New file.
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* interp.c (SignalException): Check for explicit terminating
breakpoint value.
* gencode.c: Pass instruction value through SignalException()
calls for Trap, Breakpoint and Syscall.
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