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AgeCommit message (Expand)AuthorFilesLines
1997-09-01Passify cross compilation and GCC -WallAndrew Cagney3-4/+25
1997-06-06Clean up formatting of instruction traces.Andrew Cagney1-0/+33
1997-05-29Add a simple dissasembler to igenAndrew Cagney4-38/+740
1997-05-27Extend xor-endian and per-cpu support in core module.Andrew Cagney2-0/+148
1997-05-23Preliminary suport for xor-endian suport in core module.Andrew Cagney1-1/+1
1997-05-23Incorrect test for zero-r0 code gen.Andrew Cagney2-2/+12
1997-05-16o Make tic80 insn file more `cache ready'Andrew Cagney2-0/+16
1997-05-07o Clean-up tic80 fp tracingAndrew Cagney2-3/+14
1997-05-06Add semantic tracing to the tic80Michael Meissner1-6/+5
1997-05-06Fix typo; pass trace_line request as arg; pass common stuff in static structMichael Meissner1-5/+8
1997-05-06Enable --trace-linenum supportMichael Meissner2-14/+18
1997-05-05Fix problems -Wall foundMichael Meissner3-13/+45
1997-04-30Tidy code gen.Andrew Cagney2-2/+20
1997-04-24Enable more instructions.Andrew Cagney2-24/+74
1997-04-23More Tic80 instructions.Andrew Cagney2-0/+5
1997-04-22TIc80 simulator checkpoint - runs 3 instructions - trap, addu, br.a.Andrew Cagney5-37/+546
1997-04-17 * igen.c (print_itrace): Use TRACE_FOO_P and trace_printf.David Edelsohn2-0/+655
1997-04-15 * Makefile.in (INSTALL): Set to @INSTALL@.Ian Lance Taylor1-0/+9
1997-04-03 * gen-support.c (gen_support_c): sim-state.h renamed to sim-main.h.David Edelsohn1-0/+41
1997-03-17Correctly validate 64bit instructionsAndrew Cagney2-4/+1364
1997-03-17 * configure: Re-generate.Andrew Cagney1-0/+21
1997-03-14Update namesAndrew Cagney1-0/+3
1997-03-14* ld-insn.c (parse_insn_format): Accept '*' as an alternative ofAndrew Cagney2-0/+1190
1997-03-07Loose the bugs file.Andrew Cagney1-0/+2
1997-02-21The remainder of igen taken from the PowerPC simulator directory.Andrew Cagney3-0/+632
1997-02-21Instruction decode generator taken from the PowerPC simulatorAndrew Cagney21-0/+2009
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