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2015-10-11sim: bfin: handle negative left saturated shifts as ashifts [BZ #18407]Mike Frysinger1-1/+5
When handling left saturated ashifts with negative immediates, they should be treated as right ashifts. This matches hardware behavior. Reported-by: Igor Rayak <igorr@gitatechnologies.com>
2015-06-12sim: trace: add common macros for logging infoMike Frysinger1-10/+10
The Blackfin port had some TRACE_xxx macros for easily logging trace data. Use these as a base for common ones that have a simple form and match the existing sets of helper macros.
2015-04-24Fix typos in sim sources exposed by static analysis.Nick Clifton1-1/+1
bfin PR 18273 * bfin-sim.c (decode_dsp32alu_0): Remove spurious check for s == 1. erc32 PR 18273 * exec.c (add32): Fix typo in check for overflow. igen PR 18273 * misc.c (a2i): Fix typos checking for uppercase letters.
2015-03-14sim: bfin: fix signed warningMike Frysinger1-1/+1
Fix the type of the local var to match the function it is passed to.
2015-01-01Update year range in copyright notice of all files owned by the GDB project.Joel Brobecker1-1/+1
gdb/ChangeLog: Update year range in copyright notice of all files.
2014-01-01Update Copyright year range in all files maintained by GDB.Joel Brobecker1-1/+1
2013-06-24sim: bfin: note missing parallel handling of SEARCHMike Frysinger1-0/+13
The SEARCH insn is an oddball when it comes to parallel usage. It places a big limit on what other insns it can run in parallel with, but we don't currently track the amount of state needed to verify this (since no other insn really requires this). Add a note for now in case we get around to it.
2013-06-24sim: bfin: handle invalid HLs encoding in dsp shift insnsMike Frysinger1-5/+9
For many of the 32bit dsp shift related insns, we were just ignoring the HLs field. The hardware does not though and will reject the insn if it's set incorrectly. Update the sim to match.
2013-06-19sim: bfin: stricter insn decodingMike Frysinger1-50/+81
We wrote a test case that tries every single 32bit opcode on the hardware and compared it to the sim. There were a bunch of places in the sim where we weren't strict enough (requiring certain parts of the opcode be set) so we were treating a lot of invalid opcodes as valid ones. This sprinkles out a lot additional checks in the dsp32alu class. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2013-01-01Update years in copyright notice for the GDB files.Joel Brobecker1-1/+1
Two modifications: 1. The addition of 2013 to the copyright year range for every file; 2. The use of a single year range, instead of potentially multiple year ranges, as approved by the FSF.
2012-04-09sim: bfin: fix ASTAT issues in immediate shiftsMike Frysinger1-17/+58
More ASTAT directed fixes, but this time at the dsp32shift insns. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-04-09sim: bfin: fix ASTAT/correctness issues with arithmetic shiftsMike Frysinger1-10/+60
This improves some of the arithmetic shifts to better match the hardware (especially wrt ASTAT behavior). We hit areas where the published documentation is thin so we have to rely on tests run on the hardware to figure out how things should behave. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-04-09sim: bfin: more parallel insn checksMike Frysinger1-18/+66
Now that we keep track of the exact parallel insn slot we're in, we can make sure that the current insn being decoded is valid for that slot. This brings us much closer to the hardware in flagging invalid parallel insn combinations. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-04-09sim: bfin: keep track of the exact position of parallel insnsMike Frysinger1-44/+49
Some insns need to know which slot they're in to determine whether they are valid. So add an enum for each slot, and check that rather than the overall insn len. This makes tracking things in the code much clearer. However, this code is functionally the same, so a follow up patch will leverage this more to properly flag invalid parallel insn combos. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-04-08sim: bfin: drop excess space in negation insnMike Frysinger1-1/+1
The amod1 helper includes a leading space so it can expand into the empty string when need be, which means the caller need not add spacing itself. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-04-01sim: bfin: throw VEC_ILGAL_I with 32bit insn in group1/group2 slotsMike Frysinger1-0/+3
Parallel insns can only do one 32bit, then two 16bits. So if we see a 2nd 32bit insn after the first 32bit in a parallel insn, abort. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-04-01sim: bfin: simplify field width processing and fix build warningsMike Frysinger1-10/+1
This fix the build time warning: warning: format not a string literal, argument types not checked [-Wformat-nonliteral] Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-03-19sim: bfin: fix corner case Logical shift issuesMike Frysinger1-45/+53
From: Robin Getz <robin.getz@analog.com> Overflow with shift operations happens independently of saturation, but we have the logic merged. Extend the lshift function so that callers can tell it when to handle each independently, and then do so when it's needed. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-01-04Copyright year update in most files of the GDB Project.Joel Brobecker1-1/+1
gdb/ChangeLog: Copyright year update in most files of the GDB Project.
2011-09-29sim: bfin: use store buffer for VIT_MAX insnsMike Frysinger1-2/+2
The VIT_MAX insns can be used in parallel, so we need to use the store buffer so we don't clobber the output register before we get a chance to do a memory store with it. Reported-by: Kai Iskratsch <kai@stella.at> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-18sim: bfin: set ASTAT AV/AVS when shifting accumulators overflowMike Frysinger1-0/+6
The LSHIFT/ASHIFT insns that work with accumulators lacked AV/AVS handling in the ASTAT register, so add it to match the hardware. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-18sim: bfin: do not touch ASTAT[V] when shifting accumulatorsMike Frysinger1-3/+4
If we're shifting accumulators, we don't want to touch the V bit in ASTAT, so add size checks to the ashiftrt/lshiftrt helpers. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-18sim: bfin: do not extend accumulator in LSHIFT insnsMike Frysinger1-1/+1
The logical shift insn does not sign extend before shifting, so we shouldn't either. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-18sim: bfin: tweak saturation handling with TFU/FU modes and MM bitMike Frysinger1-14/+30
This too should have been squashed into an earlier change. It covers a few more cases in the V/VS saturation patch when working with TFU and FU modes of dsp insns. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-18sim: bfin: handle large shift values with accumulator shift insnsMike Frysinger1-2/+8
When the shift magnitude exceeds 32 bits, the values rotate around (since the hardware is actually a barrel shifter). So handle this edge case, update the corresponding AV bit in ASTAT which was missing previously, and tweak the AZ setting based on how the hardware behaves. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-18sim: bfin: handle odd shift values with shift insnsMike Frysinger1-7/+29
The shift magnitude is a 5-bit signed value. When it is between 0 and 15, then we do the requested shift, but when it is outside of that, we have to do the opposite. That means we flip between lshift and ashiftrt to match the hardware. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-18sim: bfin: fix M_IH saturation sizeMike Frysinger1-12/+1
This reverts the previous commit and does it right. This change got lost in the shuffle of patches I have pending. Basically the logic is to change the 32bit saturation (and then masked to 16bits) to a proper 16bit saturation. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-18sim: bfin: handle V/VS saturation in dsp mac insnsMike Frysinger1-25/+48
Some saturation cases with dsp mac insns were not setting the V flag. So implement that part and split up the logic between the dual macs. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-18sim: bfin: handle the MM flag in M_IU/M_TFU modes with dsp insnsMike Frysinger1-0/+4
Our handling of the M_IU/M_TFU modes are missing signed saturation when the MM flag is set, so add it to match the hardware behavior. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-18sim: bfin: fix sign extension in dsp insns with MM flagMike Frysinger1-8/+3
After testing the hardware with all the different dsp flags, the MM flag triggers sign extension in all modes. So drop the limited use of it, and the local custom helper that was also extending unsigned values. We also can see that the flag checks in the mult/mac insns have the same behavior with sign extending, so add a helper func to keep the logic the same in both places. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-18sim: bfin: fix dsp insns IH saturation/rounding behaviorMike Frysinger1-1/+11
When using the IH modifier, we need to first saturate the value before rounding it, and then further saturate it a bit more. This makes the sim match the hardware behavior with these insns. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-18sim: bfin: fix accumulator edge case saturationMike Frysinger1-2/+2
When the accumulator saturates, it needs to be greater than, but not equal to, the largest unsigned value as this is what the hardware does. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-05-14sim: bfin: allow pushing of SPMike Frysinger1-2/+1
The hardware respects this insn, and some code (like the on-chip bootrom) uses it, so allow it. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-16sim: bfin: use store buffer with more 32bit insnsMike Frysinger1-23/+29
A bunch of 32bit insns were not using the store buffer, so when they were used in parallel insns, they would incorrectly clobber a register early. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-15sim: bfin: handle implicit DISALGNEXCPT with video insnsMike Frysinger1-0/+24
When most video related insns are used in parallel with Ireg loads, the DISALGNEXCPT insn behavior is implicitly in effect. Reported-by: Anton Shokurov <shokurov.anton.v@yandex.ru> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-29sim: bfin: fix sign extension with 16bit acc add insnsMike Frysinger1-9/+2
The current implementation attempts to handle the 16bit sign extension itself. Unfortunately, it gets it right in some cases. So rather than fix that logic, just drop it in favor of using 16bit signed casts. Now gcc will take care of getting the logic right. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-27sim: bfin: handle saturation with RND12 sub insnsMike Frysinger1-1/+6
The current handling of the subtraction insn with the RND12 modifier works when saturation isn't involved. So add handling for this edge case to match the hardware. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-26sim: bfin: add missing VS set with add/sub insnsMike Frysinger1-0/+3
The 16bit add/sub insns missed setting the VS bit in ASTAT whenever the V bit was also set. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24sim: bfin: update VIT_MAX behavior to match hardware when Acc.X bits are setMike Frysinger1-2/+2
The Blackfin PRM says that the top 8 bits of the accumulator must be cleared when using the VIT_MAX insn, so the sim has followed this spec. Matching the hardware behavior though when the high bits are not cleared is easy to do and doesn't break existing behavior, so go for it. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24sim: bfin: always do 16bit sign extension with the SEARCH insnMike Frysinger1-0/+5
The Blackfin PRM does not cover this case, but the hardware is clear: even if the search criteria is not met (and thus a new 16bit value is loaded up into the accumulator), the accumulator undergoes 16bit sign extension. So simply reload the low signed 16bits in that case. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24sim: bfin: update AV and AC ASTAT bits with acc negationMike Frysinger1-6/+8
The Acc=-Acc insn can overflow or carry with edge values, so make sure we update the ASTAT bits accordingly to match the hardware. Also fix a thinko where we always updated AC0 even when working with A1 regs. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24sim: bfin: allow byteop[123]p src regs to be the sameMike Frysinger1-9/+0
The hardware allows the byteop[123]p insns to use the same src reg pair, so remove the combination check in the sim. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-15sim: bfin: handle AZ updates with 16bit adds/subsMike Frysinger1-1/+1
We weren't updating AZ when doing a 16bit add or sub insn. Implement it. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-15sim: bfin: skip acc/ASTAT updates for movesMike Frysinger1-6/+6
No point in moving unchanged acc values to the acc regs, and avoid updating the acc ASTAT bits when only reading. This fixes incorrect changing of the ASTAT bits when they're only being read. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-15sim: bfin: handle AN (negative overflows) in dsp mult insnsMike Frysinger1-8/+33
The current dsp mult handler does not take care of overflows which turn values negative (and thus set AN in ASTAT). So implement it. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-15sim: bfin: handle V overflows in dsp mult insnsMike Frysinger1-7/+9
The current dsp mult handler does not take care of overflows and updating the V ASTAT bit. So implement it. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-15sim: bfin: decode ASTAT on failureMike Frysinger1-34/+72
When testing ASTAT regs, specific bit differences carry a lot more meaning than when checking the value of a data register. So automatically decode the bits of the two values and print things out so that people don't have to manually do it themselves every time. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-15sim: bfin: handle saturation with fract multiplicationsMike Frysinger1-0/+2
The saturation behavior with fract modes differs from non-fract modes. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-06sim: bfin: new portMike Frysinger1-0/+6099
This can boot Das U-Boot and a Linux kernel. It also supports Linux userspace FLAT and FDPIC (dynamic and static) ELFs. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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