| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2024-09-12 | s390: Relax risbg[n]z, risb{h|l}gz, {rns|ros|rxs}bgt operand constraints | Jens Remus | 1 | -15/+9 |
| 2024-09-12 | s390: Simplify (dis)assembly of insn operands with const bits | Jens Remus | 2 | -23/+17 |
| 2024-09-11 | x86/APX: correct disassembly for EVEX.B4 | Jan Beulich | 1 | -2/+3 |
| 2024-09-09 | s390: Align opcodes to lower-case | Jens Remus | 1 | -1/+1 |
| 2024-09-06 | x86/APX: use D for 2-operand CFCMOVcc | Jan Beulich | 2 | -577/+276 |
| 2024-09-06 | x86/APX: optimize certain reg-only CFCMOVcc forms | Jan Beulich | 2 | -31/+31 |
| 2024-09-06 | x86: templatize VNNI templates | Jan Beulich | 2 | -46/+37 |
| 2024-09-03 | RISC-V: Add support for XCVsimd extension in CV32E40P | Mary Bennett | 2 | -0/+231 |
| 2024-09-02 | Support ymm rounding control for Intel AVX10.2 | Haochen Jiang | 6 | -629/+666 |
| 2024-08-30 | x86/APX: drop %SW disassembler macro again | Jan Beulich | 2 | -17/+19 |
| 2024-08-30 | x86: limit RegRex64 use | Jan Beulich | 2 | -48/+48 |
| 2024-08-27 | RISC-V: PR32036, Support Zcmp cm.mva01s and cm.mvsa01 instructions. | Jiawei | 2 | -0/+28 |
| 2024-08-16 | opcodes/cgen: drop trailing whitespace also for cris | Jan Beulich | 2 | -48/+48 |
| 2024-08-12 | Revert "gas: have scrubber retain more whitespace" | H.J. Lu | 14 | -447/+234 |
| 2024-08-09 | gas: have scrubber retain more whitespace | Jan Beulich | 14 | -234/+447 |
| 2024-08-09 | gas: sparc: Fix faligndatai assembly and disassembly | Richard Henderson | 1 | -1/+1 |
| 2024-08-06 | RISC-V: map zext.h to pack/packw if Zbkb is enabled | Hau Hsu | 1 | -2/+2 |
| 2024-08-06 | RISC-V: Add support for XCvBitmanip extension in CV32E40P | Mary Bennett | 2 | -0/+27 |
| 2024-08-06 | RISC-V: Add support for Zcmop extension | Xiao Zeng | 1 | -0/+10 |
| 2024-08-06 | RISC-V: Add support for Zimop extension | Xiao Zeng | 1 | -0/+42 |
| 2024-07-29 | Updated translations for the bfd, binutils, gas, ld and opcodes directories | Nick Clifton | 3 | -557/+573 |
| 2024-07-26 | microMIPS: Add MT ASE instruction set support | YunQiang Su | 2 | -1/+61 |
| 2024-07-26 | x86/APX: optimize certain {nf}-form insns to BMI2 ones | Jan Beulich | 2 | -27/+27 |
| 2024-07-26 | ARM print_insn_mve assertion | Alan Modra | 1 | -17/+2 |
| 2024-07-24 | opcodes/x86: fix minor missed styling case | Andrew Burgess | 1 | -2/+2 |
| 2024-07-20 | Change version to 2.43.50 | Nick Clifton | 2 | -193/+195 |
| 2024-07-20 | Add markers for 2.43 branch/release | Nick Clifton | 1 | -0/+4 |
| 2024-07-19 | MIPS/opcodes: Replace "y" microMIPS operand code with "x" | Maciej W. Rozycki | 1 | -2/+2 |
| 2024-07-19 | MIPS/opcodes: Mark MT thread context move assembly idioms as aliases | Maciej W. Rozycki | 1 | -38/+38 |
| 2024-07-19 | MIPS/opcodes: Mark PAUSE as an alias | Maciej W. Rozycki | 1 | -1/+1 |
| 2024-07-19 | MIPS/opcodes: Reorder coprocessor moves alphabetically | Maciej W. Rozycki | 2 | -58/+62 |
| 2024-07-19 | MIPS/opcodes: Make AL a shorthand for INSN2_ALIAS | Maciej W. Rozycki | 2 | -56/+60 |
| 2024-07-19 | MIPS/opcodes: Rename the AL membership shorthand to ALX | Maciej W. Rozycki | 1 | -88/+88 |
| 2024-07-19 | MIPS/opcodes: Remove the regular MIPS "+t" operand code | YunQiang Su | 1 | -2/+1 |
| 2024-07-19 | MIPS/opcodes: Output thread context registers numerically with MFTR/MTTR | Maciej W. Rozycki | 1 | -2/+2 |
| 2024-07-19 | MIPS/opcodes: Exclude $0 from "-x" R6 operand type | Maciej W. Rozycki | 1 | -1/+1 |
| 2024-07-18 | opcodes: aarch64: enforce checks on subclass flags in aarch64-gen.c | Indu Bhagat | 1 | -0/+19 |
| 2024-07-18 | opcodes: aarch64: denote subclasses for insns of iclass dp_2src | Indu Bhagat | 1 | -24/+24 |
| 2024-07-18 | opcodes: aarch64: add flags to denote subclasses of uncond branches | Indu Bhagat | 1 | -19/+19 |
| 2024-07-18 | opcodes: aarch64: add flags to denote subclasses of arithmetic insns | Indu Bhagat | 1 | -15/+15 |
| 2024-07-18 | opcodes: aarch64: add flags to denote subclasses of ldst insns | Indu Bhagat | 1 | -43/+43 |
| 2024-07-12 | aarch64: Add support for sme2.1 zero instructions. | Srinath Parvathaneni | 3 | -208/+330 |
| 2024-07-12 | aarch64: Add support for sme2.1 movaz instructions. | Srinath Parvathaneni | 10 | -283/+493 |
| 2024-07-12 | aarch64: Add support for sme2.1 luti2 and luti4 instructions. | Srinath Parvathaneni | 4 | -210/+274 |
| 2024-07-08 | aarch64: Add support for sve2p1 pmov instruction. | srinath | 6 | -221/+409 |
| 2024-07-08 | aarch64: Add support for sve2p1 tbxq instruction. | Srinath Parvathaneni | 2 | -158/+170 |
| 2024-07-08 | aarch64: Add support for sve2p1 zipq[1-2] instructions. | Srinath Parvathaneni | 2 | -160/+184 |
| 2024-07-08 | aarch64: Add support for sve2p1 uzpq[1-2] instructions. | Srinath Parvathaneni | 2 | -151/+175 |
| 2024-07-08 | aarch64: Add support for sve2p1 tblq instruction. | Srinath Parvathaneni | 2 | -175/+187 |
| 2024-07-08 | aarch64: Add support for sve2p1 orqv instruction. | Srinath Parvathaneni | 2 | -152/+164 |
