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2022-03-16opcodes: handle bfd_amdgcn_arch in configure scriptSimon Marchi3-0/+7
2022-03-16Delete PowerPC macro insn supportAlan Modra1-18/+0
2022-03-16PowerPC SPE/SPE2 aliases in powerpc_macrosAlan Modra1-30/+27
2022-03-16PowerPC VLE extended instructions in powerpc_macrosAlan Modra1-13/+10
2022-03-16PowerPC32 extended instructions in powerpc_macrosAlan Modra1-25/+296
2022-03-16PowerPC64 extended instructions in powerpc_macrosAlan Modra1-19/+245
2022-03-14PR28959, obdump doesn't disassemble mftb instructionAlan Modra1-2/+3
2022-03-06MIPS/opcodes: Fix alias annotation for branch instructionsMaciej W. Rozycki3-7/+16
2022-02-25RISC-V: Fix mask for some fcvt instructionsTsukasa OI1-4/+4
2022-02-17Updated Serbian translations for the bfd, gold, ld and opcodes directoriesNick Clifton2-235/+275
2022-02-15x86: Add has_sib to struct instr_infoH.J. Lu1-8/+9
2022-02-14microblaze: fix fsqrt collicion to build on glibc-2.35Sergei Trofimovich3-2/+8
2022-01-24Update Bulgarian, French, Romaniam and Ukranian translation for some of the s...Nick Clifton4-923/+2834
2022-01-23Regenerate Makefile.in files with automake 1.15.1H.J. Lu1-1/+0
2022-01-23Regenerate configure files with autoconf 2.69H.J. Lu1-15/+3
2022-01-22Change version number to 2.38.50 and regenerate filesNick Clifton3-14/+31
2022-01-22Add markers for 2.38 branchNick Clifton1-0/+4
2022-01-21drop old unused stamp-h.in fileMike Frysinger1-1/+0
2022-01-17Update the config.guess and config.sub files from the master repository and r...Nick Clifton3-208/+244
2022-01-17x86: adjust struct instr_info field typesJan Beulich1-36/+39
2022-01-17x86: drop index16 fieldJan Beulich1-5/+3
2022-01-17x86: drop most Intel syntax register name arraysJan Beulich1-230/+119
2022-01-17x86: fold variables in memory operand index handlingJan Beulich1-19/+15
2022-01-17x86: constify disassembler static dataJan Beulich1-58/+58
2022-01-14x86: drop ymmxmm_modeJan Beulich1-16/+0
2022-01-14x86: share yet more VEX table entries with EVEX decodingJan Beulich4-209/+69
2022-01-14x86: consistently use scalar_mode for AVX512-FP16 scalar insnsJan Beulich2-31/+31
2022-01-14x86: record further wrong uses of EVEX.bJan Beulich1-0/+8
2022-01-14x86: reduce AVX512 FP set of insns decoded through vex_w_table[]Jan Beulich5-268/+42
2022-01-14x86: reduce AVX512-FP16 set of insns decoded through vex_w_table[]Jan Beulich4-137/+77
2022-01-06aarch64: Add support for new SME instructionsRichard Sandiford2-302/+338
2022-01-06x86: drop NoAVX insn attributeJan Beulich4-4520/+4516
2022-01-06x86: drop NoAVX from POPCNTJan Beulich2-2/+2
2022-01-06x86: drop some "comm" template parametersJan Beulich2-90/+90
2022-01-06x86: templatize FMA insn templatesJan Beulich2-1016/+830
2022-01-05opcodes: Make i386-dis.c thread-safeVladimir Mezentsev1-1738/+1774
2022-01-02Update year range in copyright notice of binutils filesAlan Modra282-286/+301
2022-01-01unify 64-bit bfd checksMike Frysinger5-4/+265
2021-12-24RISC-V: Hypervisor ext: support Privileged Spec 1.12Vineet Gupta1-0/+21
2021-12-17x86: Terminate mnemonicendp in swap_operand()Vladimir Mezentsev1-0/+1
2021-12-16RISC-V: Support svinval extension with frozen version 1.0.Nelson Chu1-0/+7
2021-12-03aarch64: Fix uninitialised memoryRichard Sandiford2-1/+3
2021-12-03Revert "Re: Don't compile some opcodes files when bfd is 32-bit only"Alan Modra2-10/+10
2021-12-02aarch64: Add BC instructionRichard Sandiford2-47/+65
2021-12-02aarch64: Enforce P/M/E order for MOPS instructionsRichard Sandiford3-15/+127
2021-12-02aarch64: Add support for +mopsRichard Sandiford9-32/+1535
2021-12-02aarch64: Add Armv8.8-A system registersRichard Sandiford1-0/+5
2021-12-02aarch64: Add id_aa64isar2_el1Richard Sandiford1-0/+1
2021-12-02aarch64: Tweak insn sequence codeRichard Sandiford1-26/+22
2021-12-02aarch64: Add maximum immediate value to aarch64_sys_regRichard Sandiford2-35/+26
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