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2016-12-28Check bfd support for bfd_mips_elf_get_abiflags in mips make ruleAlan Modra7-132/+38
2016-12-23MIPS16: Add ASMACRO instruction supportMaciej W. Rozycki2-0/+15
2016-12-23MIPS16: Simplify extended operand handlingMaciej W. Rozycki3-20/+25
2016-12-23MIPS16: Reassign `0' and `4' operand codesMaciej W. Rozycki2-15/+22
2016-12-23MIPS16: Handle non-extensible instructions correctlyMaciej W. Rozycki3-68/+86
2016-12-23MIPS16: Remove "extended" BREAK/SDBBP handlingMaciej W. Rozycki2-2/+6
2016-12-23MIPS16/GAS: Disallow EXTEND delay-slot schedulingMaciej W. Rozycki2-1/+6
2016-12-23opcodes: Use autoconf to check for `bfd_mips_elf_get_abiflags' in BFDMaciej W. Rozycki8-12/+150
2016-12-23Bump version to 2.28.51Tristan Gingold2-10/+14
2016-12-23Regenerate pot files.Tristan Gingold2-372/+640
2016-12-22ChangeLog formatting fixesAlan Modra1-1/+1
2016-12-22Avoid creating symbol table entries for registersAndrew Waterman2-2/+6
2016-12-20MIPS16/opcodes: Respect ISA and ASE in disassemblyMaciej W. Rozycki2-1/+11
2016-12-20MIPS16: Switch to 32-bit opcode table interpretationMaciej W. Rozycki3-81/+90
2016-12-20MIPS16/opcodes: Correct 64-bit macros' ISA membershipMaciej W. Rozycki2-6/+12
2016-12-20MIPS16/opcodes: Correct I64/SDRASP opcode's ISA membershipMaciej W. Rozycki2-1/+7
2016-12-20Correct assembler mnemonic for RISC-V aqrl AMOsAndrew Waterman2-22/+27
2016-12-20Fix disassembly of RISC-V CSR instructions under -Mno-aliasesAndrew Waterman2-22/+27
2016-12-20Add canonical JALR for RISC-VAndrew Waterman2-0/+8
2016-12-20Re-work RISC-V gas flags: now we just support -mabi and -marchAndrew Waterman2-2/+11
2016-12-20Formatting changes for RISC-VAndrew Waterman2-8/+10
2016-12-20Add opcodes RISC-V dependenciesAlan Modra4-0/+14
2016-12-19MIPS/opcodes: Only examine ELF file structures if SYMTAB_AVAILABLEMaciej W. Rozycki2-1/+6
2016-12-19MIPS/opcodes: Only call `bfd_mips_elf_get_abiflags' if BFD64Maciej W. Rozycki2-2/+14
2016-12-16Fix compile time warning building arm-dis.cNick Clifton2-2/+7
2016-12-14MIPS/opcodes: Also set disassembler's ASE flags from ELF structuresMaciej W. Rozycki2-2/+48
2016-12-14MIPS/opcodes: Reorder ELF file header flag handling in disassemblerMaciej W. Rozycki2-13/+18
2016-12-14MIPS16: Fix SP-relative SD instruction annotationMaciej W. Rozycki2-2/+7
2016-12-14MIPS16/opcodes: Fix and clarify MIPS16e commentaryMaciej W. Rozycki2-4/+9
2016-12-13[Binutils][AARCH64]Remove Cn register for coprocessor CRn, CRm fieldRenlin Li6-25/+29
2016-12-12Handle memory error in print_insn_rxYao Qi2-4/+36
2016-12-12Handle memory error in print_insn_rl78_commonYao Qi2-4/+36
2016-12-09MIPS16: Remove unused `>' operand codeMaciej W. Rozycki2-2/+4
2016-12-09MIPS16/opcodes: Use hexadecimal interpretation for the `e' operand codeMaciej W. Rozycki2-1/+6
2016-12-09MIPS16/opcodes: Reformat raw EXTEND and undecoded outputMaciej W. Rozycki2-4/+11
2016-12-08MIPS16/opcodes: Fix off-by-one indentation in `print_mips16_insn_arg'Maciej W. Rozycki2-30/+35
2016-12-08MIPS16/opcodes: Fix PC-relative operation delay-slot adjustmentMaciej W. Rozycki2-6/+16
2016-12-08AArch64/opcodes: Correct another `index' global shadowing errorMaciej W. Rozycki2-8/+13
2016-12-08Fix crash when disassembling invalid range on powerpc vleLuis Machado2-1/+5
2016-12-07MIPS/opcodes: Correct an `interaction' comment typoMaciej W. Rozycki2-1/+5
2016-12-07MIPS16/opcodes: Update opcode table commentMaciej W. Rozycki2-1/+6
2016-12-07MIPS/opcodes: Reformat `-M' disassembler option's help textMaciej W. Rozycki2-5/+10
2016-12-05[ARM] Add ARMv8.3 VCMLA and VCADD instructionsSzabolcs Nagy2-0/+33
2016-12-05[ARM] Add ARMv8.3 VJCVT instructionSzabolcs Nagy2-0/+8
2016-12-01Fix abort in x86 disassembler.Nick Clifton2-1/+8
2016-11-29[ARC] Add checking for LP_COUNT reg usage, improve error reporting.Claudiu Zissulescu4-2264/+2341
2016-11-29[ARC] Fix disassembler option.Claudiu Zissulescu2-55/+48
2016-11-28X86: Ignore REX_B bit for 32-bit XOP instructionsAmit Pawar2-4/+15
2016-11-22Fix spelling mistakes in comments in configure scriptsAmbrogino Modigliani2-1/+5
2016-11-22gas,opcodes: fix hardware capabilities bumping in the sparc assembler.Jose E. Marchesi2-15/+50
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