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2017-01-20Updated Irish translation for the opcodes library.Nick Clifton2-458/+813
2017-01-18[ARM] Fix the decoding of indexed element VCMLA instructionSzabolcs Nagy2-4/+8
2017-01-13Return -1 on memory error in print_insn_m68kYao Qi2-7/+19
2017-01-13Remove magic numbers in m68k-dis.c:print_insn_argYao Qi2-41/+72
2017-01-12Enable Intel AVX512_VPOPCNTDQ instructionsIgor Tsimbalist8-5344/+5432
2017-01-12Return -1 on memory error in print_insn_msp430Yao Qi2-14/+99
2017-01-05Prevent an abort in the FRV disassembler if the target bfd name is unknown.Nick Clifton2-3/+11
2017-01-04[AArch64] Add separate feature flag for weaker release consistent load insnsSzabolcs Nagy2-3/+13
2017-01-03Add support for the Q extension to the RISCV ISA.Kito Cheng2-0/+66
2017-01-03Add fall through comment.Dilyan Palauzov2-0/+5
2017-01-03Add new Serbian translation for the opcodes library.Nick Clifton4-2/+1515
2017-01-02Regen opcodes cgen filesAlan Modra27-0/+237
2017-01-02Update year range in copyright notice of all files.Alan Modra275-278/+282
2017-01-02ChangeLog rotationAlan Modra2-2167/+2181
2016-12-31Fix riscv breakageAlan Modra2-0/+6
2016-12-31PRU Opcode PortDimitar Dimitrov9-1/+548
2016-12-29Return 'int' rather than 'unsigned short' in avrdis_opcodeYao Qi2-6/+23
2016-12-28Check bfd support for bfd_mips_elf_get_abiflags in mips make ruleAlan Modra7-132/+38
2016-12-23MIPS16: Add ASMACRO instruction supportMaciej W. Rozycki2-0/+15
2016-12-23MIPS16: Simplify extended operand handlingMaciej W. Rozycki3-20/+25
2016-12-23MIPS16: Reassign `0' and `4' operand codesMaciej W. Rozycki2-15/+22
2016-12-23MIPS16: Handle non-extensible instructions correctlyMaciej W. Rozycki3-68/+86
2016-12-23MIPS16: Remove "extended" BREAK/SDBBP handlingMaciej W. Rozycki2-2/+6
2016-12-23MIPS16/GAS: Disallow EXTEND delay-slot schedulingMaciej W. Rozycki2-1/+6
2016-12-23opcodes: Use autoconf to check for `bfd_mips_elf_get_abiflags' in BFDMaciej W. Rozycki8-12/+150
2016-12-23Bump version to 2.28.51Tristan Gingold2-10/+14
2016-12-23Regenerate pot files.Tristan Gingold2-372/+640
2016-12-22ChangeLog formatting fixesAlan Modra1-1/+1
2016-12-22Avoid creating symbol table entries for registersAndrew Waterman2-2/+6
2016-12-20MIPS16/opcodes: Respect ISA and ASE in disassemblyMaciej W. Rozycki2-1/+11
2016-12-20MIPS16: Switch to 32-bit opcode table interpretationMaciej W. Rozycki3-81/+90
2016-12-20MIPS16/opcodes: Correct 64-bit macros' ISA membershipMaciej W. Rozycki2-6/+12
2016-12-20MIPS16/opcodes: Correct I64/SDRASP opcode's ISA membershipMaciej W. Rozycki2-1/+7
2016-12-20Correct assembler mnemonic for RISC-V aqrl AMOsAndrew Waterman2-22/+27
2016-12-20Fix disassembly of RISC-V CSR instructions under -Mno-aliasesAndrew Waterman2-22/+27
2016-12-20Add canonical JALR for RISC-VAndrew Waterman2-0/+8
2016-12-20Re-work RISC-V gas flags: now we just support -mabi and -marchAndrew Waterman2-2/+11
2016-12-20Formatting changes for RISC-VAndrew Waterman2-8/+10
2016-12-20Add opcodes RISC-V dependenciesAlan Modra4-0/+14
2016-12-19MIPS/opcodes: Only examine ELF file structures if SYMTAB_AVAILABLEMaciej W. Rozycki2-1/+6
2016-12-19MIPS/opcodes: Only call `bfd_mips_elf_get_abiflags' if BFD64Maciej W. Rozycki2-2/+14
2016-12-16Fix compile time warning building arm-dis.cNick Clifton2-2/+7
2016-12-14MIPS/opcodes: Also set disassembler's ASE flags from ELF structuresMaciej W. Rozycki2-2/+48
2016-12-14MIPS/opcodes: Reorder ELF file header flag handling in disassemblerMaciej W. Rozycki2-13/+18
2016-12-14MIPS16: Fix SP-relative SD instruction annotationMaciej W. Rozycki2-2/+7
2016-12-14MIPS16/opcodes: Fix and clarify MIPS16e commentaryMaciej W. Rozycki2-4/+9
2016-12-13[Binutils][AARCH64]Remove Cn register for coprocessor CRn, CRm fieldRenlin Li6-25/+29
2016-12-12Handle memory error in print_insn_rxYao Qi2-4/+36
2016-12-12Handle memory error in print_insn_rl78_commonYao Qi2-4/+36
2016-12-09MIPS16: Remove unused `>' operand codeMaciej W. Rozycki2-2/+4
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