| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2024-03-28 | x86: templatize RAO-INT insns | Jan Beulich | 1 | -8/+4 |
| 2024-03-28 | x86: templatize ADX insns | Jan Beulich | 1 | -6/+5 |
| 2024-03-28 | x86: templatize shift-double insns | Jan Beulich | 2 | -331/+303 |
| 2024-03-28 | x86: templatize shift/rotate insns | Jan Beulich | 2 | -264/+379 |
| 2024-03-28 | x86: templatize binary ALU insns | Jan Beulich | 2 | -449/+473 |
| 2024-03-28 | x86: templatize unary ALU insns | Jan Beulich | 2 | -16/+22 |
| 2024-03-28 | x86: templatize INC/DEC | Jan Beulich | 3 | -68/+80 |
| 2024-03-19 | gas, aarch64: Add faminmax extension | Saurabh Jha | 4 | -2486/+2626 |
| 2024-03-18 | Regenerate AArch64 opcodes files | Nick Clifton | 3 | -468/+583 |
| 2024-03-18 | aarch64: Add support for SVE ADDPT, SUBPT, MADPT, MLAPT instructions | Yury Khrustalev | 1 | -0/+18 |
| 2024-03-18 | aarch64: Add support for (M)ADDPT and (M)SUBPT instructions | Yury Khrustalev | 6 | -1/+78 |
| 2024-03-18 | Arm64: check matching operands for predicated B16B16 insns | Jan Beulich | 2 | -17/+17 |
| 2024-03-18 | Arm64: correct B16B16 indexed bf{mla,mls,mul} | Jan Beulich | 1 | -3/+3 |
| 2024-03-15 | x86/APX: legacy promoted insns can't access %xmm16-%xmm31 | Jan Beulich | 1 | -0/+5 |
| 2024-03-13 | opcodes: Fix build verbosity | Christophe Lyon | 2 | -8/+8 |
| 2024-03-08 | RISC-V: Support Zabha extension. | Jiawei | 1 | -0/+74 |
| 2024-03-01 | s390: Print base register 0 as "0" in disassembly | Jens Remus | 1 | -4/+13 |
| 2024-03-01 | s390: Warn when register name type does not match operand | Jens Remus | 1 | -31/+31 |
| 2024-03-01 | s390: Add test cases for base/index register 0 | Jens Remus | 1 | -2/+3 |
| 2024-03-01 | s390: Use proper string lengths when parsing opcode table flags | Jens Remus | 1 | -3/+3 |
| 2024-03-01 | s390: Whitespace fixes in conditional branch flavor descriptions | Jens Remus | 1 | -3/+3 |
| 2024-03-01 | x86/APX: optimize certain XOR and SUB forms | Jan Beulich | 2 | -4/+4 |
| 2024-02-29 | aarch64: Fix the 2nd operand in gcsstr and gcssttr instructions. | Srinath Parvathaneni | 1 | -2/+2 |
| 2024-02-29 | PR21739, Inconsistent diagnostics | Alan Modra | 1 | -0/+2 |
| 2024-02-29 | RISC-V: Add assembly support for TLSDESC. | Tatsuyuki Ishi | 1 | -0/+1 |
| 2024-02-27 | aarch64: rename internals related to PAuth feature to use pauth in their nami... | Matthieu Longo | 1 | -38/+38 |
| 2024-02-23 | x86: also permit YMM/ZMM use in CFI directives | Jan Beulich | 2 | -128/+129 |
| 2024-02-23 | x86/APX: INV{EPT,PCID,VPID} are WIG | Jan Beulich | 2 | -6/+6 |
| 2024-02-20 | kvx: gas: missing aliases for $r14r15 in assembler. | Paul Iannetta | 1 | -10653/+10659 |
| 2024-02-20 | kvx: enable magic immediates for integer multiply-accumulate and CMOVE* | Paul Iannetta | 1 | -39/+1490 |
| 2024-02-20 | kvx: gas: rename: or -> ior, xor -> eor | Paul Iannetta | 1 | -2396/+5257 |
| 2024-02-20 | kvx: gas: move the splat modifier to the immediate | Paul Iannetta | 1 | -1083/+1134 |
| 2024-02-19 | aarch64: Add support for the id_aa64isar3_el1 system register | Yury Khrustalev | 1 | -0/+1 |
| 2024-02-16 | x86/APX: drop stray IgnoreSize | Jan Beulich | 2 | -22/+22 |
| 2024-02-16 | x86: don't use VexWIG in SSE2AVX templates | Jan Beulich | 2 | -8/+8 |
| 2024-02-16 | x86: drop redundant Xmmword | Jan Beulich | 1 | -8/+8 |
| 2024-02-15 | objdump, as: add callx support for BPF CPU v1 | Will Hawkins | 2 | -1/+5 |
| 2024-02-14 | arc: Put DBNZ instruction to a separate class | Yuriy Kolerov | 3 | -1/+7 |
| 2024-02-09 | PowerPC: Add support for Power11 options | Peter Bergner | 1 | -1/+11 |
| 2024-02-09 | x86/APX: with REX2 map 1 doesn't "chain" to maps 2 or 3 | Jan Beulich | 1 | -7/+5 |
| 2024-02-09 | x86/APX: V{BROADCAST,EXTRACT,INSERT}{F,I}128 can also be expressed | Jan Beulich | 2 | -201/+285 |
| 2024-02-09 | x86/APX: VROUND{P,S}{S,D} encodings require AVX512{F,VL} | Jan Beulich | 2 | -6/+6 |
| 2024-02-09 | x86: change type of Dwarf2 register numbers in register table | Jan Beulich | 1 | -2/+2 |
| 2024-01-29 | bpf: there is no ldinddw nor ldabsdw instructions | Jose E. Marchesi | 2 | -4/+5 |
| 2024-01-26 | aarch64: move SHA512 instructions to +sha3 | Andrew Carlotti | 1 | -5/+5 |
| 2024-01-26 | x86/APX: TILE{RELEASE,ZERO} have no EVEX encodings | Jan Beulich | 2 | -2/+11 |
| 2024-01-26 | x86/APX: no need to have decode go through x86_64_table[] | Jan Beulich | 3 | -76/+27 |
| 2024-01-26 | x86/APX: optimize MOVBE | Jan Beulich | 2 | -36/+38 |
| 2024-01-26 | LoongArch: gas: Add support for s9 register | mengqinggang | 1 | -0/+9 |
| 2024-01-24 | aarch64: Eliminate unused variable warnings with -DNDEBUG | Andrew Carlotti | 3 | -8/+8 |
