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2020-05-11Power10 VSX scalar min-max-compare quad precision operationsAlan Modra2-0/+16
2020-05-11Power10 VSX load/store rightmost element operationsAlan Modra2-0/+21
2020-05-11Power10 test lsb by byte operationAlan Modra2-0/+5
2020-05-11Power10 string operationsAlan Modra2-0/+15
2020-05-11Power10 Set boolean extensionPeter Bergner2-0/+13
2020-05-11Power10 bit manipulation operationsAlan Modra2-1/+27
2020-05-11Power10 VSX PCV generate operationsAlan Modra2-0/+9
2020-05-11Power10 VSX Mask Manipulation OperationsAlan Modra2-1/+36
2020-05-11Power10 Reduced precision outer product operationsAlan Modra3-4/+231
2020-05-11Power10 SIMD permute class operationsAlan Modra2-3/+129
2020-05-11Power10 128-bit binary integer operationsAlan Modra2-0/+44
2020-05-11Power10 VSX 32-byte storage accessAlan Modra2-1/+44
2020-05-11Power10 vector integer multiply, divide, modulo insnsAlan Modra2-0/+23
2020-05-11Power10 byte reverse instructionsPeter Bergner2-0/+10
2020-05-11Power10 Copy/Paste ExtensionsPeter Bergner2-2/+37
2020-05-11Power10 Add new L operand to the slbiag instructionPeter Bergner2-1/+7
2020-05-11PowerPC Default disassembler to -Mpower10Alan Modra2-1/+5
2020-05-11PowerPC Rename powerxx to power10Alan Modra3-30/+41
2020-05-11Updated French translation for the ld sub-directory and an update Spanish tra...Nick Clifton2-349/+455
2020-04-30AArch64: add GAS support for UDF instructionAlex Coplan8-2477/+2541
2020-04-29Also use unsigned 8-bit immediate values for the LDRC and SETRC insns.Nick Clifton2-2/+8
2020-04-29Updated Serbian translation for the binutils sub-directory, and Swedish trans...Nick Clifton2-351/+457
2020-04-29Fix the disassmbly of SH instructions which have an unsigned 8-bit immediate ...Nick Clifton3-18/+31
2020-04-21Disallow PC relative for CMPI on MC68000/10Andreas Schwab2-6/+18
2020-04-20[AArch64, Binutils] Add missing TSB instructionSudakshina Das10-1376/+1422
2020-04-20[AArch64, Binutils] Make hint space instructions valid for Armv8-aSudakshina Das5-1370/+1369
2020-04-17[PATCH v2] binutils: arm: Fix disassembly of conditional VDUPs.Fredrik Strupe2-10/+53
2020-04-16cpu,gas,opcodes: support for eBPF JMP32 instruction classDavid Faust5-13/+515
2020-04-07Add support for intel TSXLDTRK instructions$Cui,Lili7-4154/+4234
2020-04-02Add support for intel SERIALIZE instructionLiliCui7-4151/+4205
2020-03-26Re: H8300 use of uninitialised valueAlan Modra4-126/+152
2020-03-26Re: ARC: Use of uninitialised valueAlan Modra2-2/+6
2020-03-25Uninitialised memory read in z80-dis.cAlan Modra2-0/+5
2020-03-22H8300 use of uninitialised valueAlan Modra2-6/+33
2020-03-22ARC: Use of uninitialised valueAlan Modra2-3/+10
2020-03-22NS32K arg_bufs uninitialisedAlan Modra2-9/+17
2020-03-22s12z disassembler tidyAlan Modra3-315/+760
2020-03-20metag uninitialized memory readAlan Modra2-2/+13
2020-03-20NDS32 disassembly of odd sized sectionsAlan Modra2-9/+22
2020-03-20PowerPC disassembly of odd sized sectionsAlan Modra2-10/+25
2020-03-17Replace a couple of assertions in the BFD library that can be triggered by at...Nick Clifton1-0/+5
2020-03-17Fix a small set of Z80 problems.Sergey Belyashov1-19/+8
2020-03-13x86-64: correct mis-named X86_64_0D enumeratorJan Beulich2-3/+8
2020-03-09x86: Also pass -P to $(CPP) when processing i386-opc.tblH.J. Lu3-2/+7
2020-03-09x86: use template for AVX512 integer comparison insnsJan Beulich3-80/+48
2020-03-09x86: use template for XOP integer comparison, shift, and rotate insnsJan Beulich3-268/+187
2020-03-09x86: use template for AVX/AVX512 floating point comparison insnsJan Beulich3-3877/+4305
2020-03-09x86: use template for SSE floating point comparison insnsJan Beulich4-208/+165
2020-03-09x86: allow opcode templates to be templatedJan Beulich4-151/+298
2020-03-06x86: reduce amount of various VCVT* templatesJan Beulich3-237/+93
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